| Message ID | 1513098921-21042-1-git-send-email-jassisinghbrar@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | Socionext Synquacer NETSEC driver | expand |
Hi, On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghbrar@gmail.com wrote: > From: Jassi Brar <jassisinghbrar@gmail.com> > > This patch adds documentation for Device-Tree bindings for the > Socionext NetSec Controller driver. > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> > --- > .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt > > diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt > new file mode 100644 > index 0000000..4695969 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt > @@ -0,0 +1,45 @@ > +* Socionext NetSec Ethernet Controller IP > + > +Required properties: > +- compatible: Should be "socionext,synquacer-netsec" > +- reg: Address and length of the control register area, followed by the > + address and length of the EEPROM holding the MAC address and > + microengine firmware > +- interrupts: Should contain ethernet controller interrupt > +- clocks: phandle to the PHY reference clock, and any other clocks to be > + switched by runtime_pm > +- clock-names: Required only if more than a single clock is listed in 'clocks'. > + The PHY reference clock must be named 'phy_refclk' Please define the full set of clocks (and their names) explicitly. This should be well-known. Otherwise, this looks ok. Thanks, Mark. > +- phy-mode: See ethernet.txt file in the same directory > +- phy-handle: phandle to select child phy > + > +Optional properties: (See ethernet.txt file in the same directory) > +- dma-coherent: Boolean property, must only be present if memory > + accesses performed by the device are cache coherent > +- local-mac-address > +- mac-address > +- max-speed > +- max-frame-size > + > +Required properties for the child phy: > +- reg: phy address > + > +Example: > + eth0: netsec@522D0000 { > + compatible = "socionext,synquacer-netsec"; > + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_netsec>; > + phy-mode = "rgmii"; > + max-speed = <1000>; > + max-frame-size = <9000>; > + phy-handle = <ðphy0>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + ethphy0: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > + }; > -- > 2.7.4 >
On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghbrar@gmail.com wrote: > From: Jassi Brar <jassisinghbrar@gmail.com> > > This patch adds documentation for Device-Tree bindings for the > Socionext NetSec Controller driver. > > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> > --- > .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt > > diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt > new file mode 100644 > index 0000000..4695969 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt > @@ -0,0 +1,45 @@ > +* Socionext NetSec Ethernet Controller IP > + > +Required properties: > +- compatible: Should be "socionext,synquacer-netsec" > +- reg: Address and length of the control register area, followed by the > + address and length of the EEPROM holding the MAC address and > + microengine firmware > +- interrupts: Should contain ethernet controller interrupt > +- clocks: phandle to the PHY reference clock, and any other clocks to be > + switched by runtime_pm > +- clock-names: Required only if more than a single clock is listed in 'clocks'. > + The PHY reference clock must be named 'phy_refclk' > +- phy-mode: See ethernet.txt file in the same directory > +- phy-handle: phandle to select child phy > + > +Optional properties: (See ethernet.txt file in the same directory) > +- dma-coherent: Boolean property, must only be present if memory > + accesses performed by the device are cache coherent > +- local-mac-address > +- mac-address > +- max-speed > +- max-frame-size > + > +Required properties for the child phy: > +- reg: phy address Hi Jassi Just reference phy.txt > + > +Example: > + eth0: netsec@522D0000 { > + compatible = "socionext,synquacer-netsec"; > + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_netsec>; > + phy-mode = "rgmii"; > + max-speed = <1000>; > + max-frame-size = <9000>; > + phy-handle = <ðphy0>; > + > + #address-cells = <1>; > + #size-cells = <0>; > + Please add an mdio node here, and list all the phys and possibly Ethernet switches as children of it. Andrew
Hi Mark, On Tue, Dec 12, 2017 at 10:59 PM, Mark Rutland <mark.rutland@arm.com> wrote: > Hi, > > On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghbrar@gmail.com wrote: >> From: Jassi Brar <jassisinghbrar@gmail.com> >> >> This patch adds documentation for Device-Tree bindings for the >> Socionext NetSec Controller driver. >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> >> --- >> .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt >> >> diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt >> new file mode 100644 >> index 0000000..4695969 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt >> @@ -0,0 +1,45 @@ >> +* Socionext NetSec Ethernet Controller IP >> + >> +Required properties: >> +- compatible: Should be "socionext,synquacer-netsec" >> +- reg: Address and length of the control register area, followed by the >> + address and length of the EEPROM holding the MAC address and >> + microengine firmware >> +- interrupts: Should contain ethernet controller interrupt >> +- clocks: phandle to the PHY reference clock, and any other clocks to be >> + switched by runtime_pm >> +- clock-names: Required only if more than a single clock is listed in 'clocks'. >> + The PHY reference clock must be named 'phy_refclk' > > Please define the full set of clocks (and their names) explicitly. This > should be well-known. > The issue is some implementations have just the 'rate-reference' clock going in, while others may also have 1or2 optional 'enable' clocks (which may go to other devices as well). The driver only needs to know which clock to read the freq from, so it expects that clock to be named 'phy_refclk', while the 'enable' clocks can be named anything. Thanks
On 13 December 2017 at 02:07, Andrew Lunn <andrew@lunn.ch> wrote: > On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghbrar@gmail.com wrote: >> From: Jassi Brar <jassisinghbrar@gmail.com> >> >> This patch adds documentation for Device-Tree bindings for the >> Socionext NetSec Controller driver. >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> >> --- >> .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt >> >> diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt >> new file mode 100644 >> index 0000000..4695969 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt >> @@ -0,0 +1,45 @@ >> +* Socionext NetSec Ethernet Controller IP >> + >> +Required properties: >> +- compatible: Should be "socionext,synquacer-netsec" >> +- reg: Address and length of the control register area, followed by the >> + address and length of the EEPROM holding the MAC address and >> + microengine firmware >> +- interrupts: Should contain ethernet controller interrupt >> +- clocks: phandle to the PHY reference clock, and any other clocks to be >> + switched by runtime_pm >> +- clock-names: Required only if more than a single clock is listed in 'clocks'. >> + The PHY reference clock must be named 'phy_refclk' >> +- phy-mode: See ethernet.txt file in the same directory >> +- phy-handle: phandle to select child phy >> + >> +Optional properties: (See ethernet.txt file in the same directory) >> +- dma-coherent: Boolean property, must only be present if memory >> + accesses performed by the device are cache coherent >> +- local-mac-address >> +- mac-address >> +- max-speed >> +- max-frame-size >> + >> +Required properties for the child phy: >> +- reg: phy address > > Hi Jassi > > Just reference phy.txt > >> + >> +Example: >> + eth0: netsec@522D0000 { >> + compatible = "socionext,synquacer-netsec"; >> + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; >> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&clk_netsec>; >> + phy-mode = "rgmii"; >> + max-speed = <1000>; >> + max-frame-size = <9000>; >> + phy-handle = <ðphy0>; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + > > Please add an mdio node here, and list all the phys and possibly > Ethernet switches as children of it. > OK. Though in order to avoid breaking dtbs in the wild already, the driver falls back on using the parent node if no mdio subnode is found. Thank you.
On Wed, Dec 20, 2017 at 2:02 AM, Jassi Brar <jassisinghbrar@gmail.com> wrote: > Hi Mark, > > On Tue, Dec 12, 2017 at 10:59 PM, Mark Rutland <mark.rutland@arm.com> wrote: >> Hi, >> >> On Tue, Dec 12, 2017 at 10:45:21PM +0530, jassisinghbrar@gmail.com wrote: >>> From: Jassi Brar <jassisinghbrar@gmail.com> >>> >>> This patch adds documentation for Device-Tree bindings for the >>> Socionext NetSec Controller driver. >>> >>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >>> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> >>> --- >>> .../devicetree/bindings/net/socionext-netsec.txt | 43 ++++++++++++++++++++++ >>> 1 file changed, 43 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/net/socionext-netsec.txt >>> >>> diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt >>> new file mode 100644 >>> index 0000000..4695969 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt >>> @@ -0,0 +1,45 @@ >>> +* Socionext NetSec Ethernet Controller IP >>> + >>> +Required properties: >>> +- compatible: Should be "socionext,synquacer-netsec" >>> +- reg: Address and length of the control register area, followed by the >>> + address and length of the EEPROM holding the MAC address and >>> + microengine firmware >>> +- interrupts: Should contain ethernet controller interrupt >>> +- clocks: phandle to the PHY reference clock, and any other clocks to be >>> + switched by runtime_pm runtime_pm is a Linux thing and driver detail. >>> +- clock-names: Required only if more than a single clock is listed in 'clocks'. >>> + The PHY reference clock must be named 'phy_refclk' >> >> Please define the full set of clocks (and their names) explicitly. This >> should be well-known. >> > The issue is some implementations have just the 'rate-reference' clock > going in, while others may also have 1or2 optional 'enable' clocks > (which may go to other devices as well). > The driver only needs to know which clock to read the freq from, so it > expects that clock to be named 'phy_refclk', while the 'enable' clocks > can be named anything. It still needs to be documented. If there's differing number of clocks, then I expect a compatible string for each possible clock setup. Of course, differing number of clocks for the same block is often an error when multiple clock inputs are driven by the same source clock. Rob
diff --git a/Documentation/devicetree/bindings/net/socionext-netsec.txt b/Documentation/devicetree/bindings/net/socionext-netsec.txt new file mode 100644 index 0000000..4695969 --- /dev/null +++ b/Documentation/devicetree/bindings/net/socionext-netsec.txt @@ -0,0 +1,45 @@ +* Socionext NetSec Ethernet Controller IP + +Required properties: +- compatible: Should be "socionext,synquacer-netsec" +- reg: Address and length of the control register area, followed by the + address and length of the EEPROM holding the MAC address and + microengine firmware +- interrupts: Should contain ethernet controller interrupt +- clocks: phandle to the PHY reference clock, and any other clocks to be + switched by runtime_pm +- clock-names: Required only if more than a single clock is listed in 'clocks'. + The PHY reference clock must be named 'phy_refclk' +- phy-mode: See ethernet.txt file in the same directory +- phy-handle: phandle to select child phy + +Optional properties: (See ethernet.txt file in the same directory) +- dma-coherent: Boolean property, must only be present if memory + accesses performed by the device are cache coherent +- local-mac-address +- mac-address +- max-speed +- max-frame-size + +Required properties for the child phy: +- reg: phy address + +Example: + eth0: netsec@522D0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522D0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_netsec>; + phy-mode = "rgmii"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <ðphy0>; + + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + };