diff mbox series

[U-Boot,v2] armv8: layerscape: sata: refine port register configuration

Message ID 20171211051209.47158-1-andy.tang@nxp.com
State Accepted
Delegated to: York Sun
Headers show
Series [U-Boot,v2] armv8: layerscape: sata: refine port register configuration | expand

Commit Message

Andy Tang Dec. 11, 2017, 5:12 a.m. UTC 
Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively.
Calculate those parameters from port clock frequency. Overwrite those
registers with calculated values to get better OOB timing.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v2:
    - refine the commit message and title

 arch/arm/cpu/armv8/fsl-layerscape/soc.c        | 6 ++++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
 2 files changed, 8 insertions(+)

Comments

York Sun Jan. 11, 2018, 7:35 p.m. UTC | #1 
On 12/10/2017 09:31 PM, Yuantian Tang wrote:
> Sata registers PP2C and PP3C are used to control the configuration
> of the PHY control OOB timing for the COMINIT/COMWAKE parameters
> respectively.
> Calculate those parameters from port clock frequency. Overwrite those
> registers with calculated values to get better OOB timing.
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> ---
> v2:
>     - refine the commit message and title
> 

Applied to fsl-qoriq master. Thanks.

York
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 497a4b541d..b52653929c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -328,6 +328,8 @@  int sata_init(void)
 #ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -335,6 +337,8 @@  int sata_init(void)
 #ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -355,6 +359,8 @@  int sata_init(void)
 	/* Disable SATA ECC */
 	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..664d847e9c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@  struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
+#define AHCI_PORT_PHY2_CFG	0x28184d1f
+#define AHCI_PORT_PHY3_CFG	0x0e081509
 #define AHCI_PORT_TRANS_CFG    0x08000029
 #define AHCI_PORT_AXICC_CFG	0x3fffffff