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[2001:470:b8f6:1b::1]) by smtp.gmail.com with ESMTPSA id i11sm9963116pfk.25.2017.12.07.13.46.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Dec 2017 13:46:30 -0800 (PST) Received: from t430.minyard.net (t430m.minyard.net [192.168.27.3]) by serve.minyard.net (Postfix) with ESMTPA id 9A4DDEE8; Thu, 7 Dec 2017 15:46:25 -0600 (CST) Received: by t430.minyard.net (Postfix, from userid 1000) id 43072302367; Thu, 7 Dec 2017 15:46:23 -0600 (CST) From: minyard@acm.org To: qemu-devel@nongnu.org Date: Thu, 7 Dec 2017 15:46:14 -0600 Message-Id: <1512683181-8420-8-git-send-email-minyard@acm.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512683181-8420-1-git-send-email-minyard@acm.org> References: <1512683181-8420-1-git-send-email-minyard@acm.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 07/14] i2c:pm_smbus: Add the ability to force block transfer enable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , Paolo Bonzini , "Michael S . Tsirkin" Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Corey Minyard The PIIX4 hardware has block transfer buffer always enabled in the hardware, but the i801 does not. Add a parameter to pm_smbus_init to force on the block transfer so the PIIX4 handler can enable this by default, as it was disabled by default before. Signed-off-by: Corey Minyard Cc: Michael S. Tsirkin Cc: Paolo Bonzini --- hw/acpi/piix4.c | 2 +- hw/i2c/pm_smbus.c | 5 ++++- hw/i2c/smbus_ich9.c | 2 +- hw/isa/vt82c686.c | 2 +- include/hw/i2c/pm_smbus.h | 2 +- 5 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 18c1ffa..7018235 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -514,7 +514,7 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) pci_conf[0x90] = s->smb_io_base | 1; pci_conf[0x91] = s->smb_io_base >> 8; pci_conf[0xd2] = 0x09; - pm_smbus_init(DEVICE(dev), &s->smb); + pm_smbus_init(DEVICE(dev), &s->smb, true); memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1); memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base, &s->smb.io); diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 2fb00d0..2afc5e1 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -401,11 +401,14 @@ const VMStateDescription pmsmb_vmstate = { } }; -void pm_smbus_init(DeviceState *parent, PMSMBus *smb) +void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk) { smb->op_done = true; smb->reset = pm_smbus_reset; smb->smbus = i2c_init_bus(parent, "i2c"); + if (force_aux_blk) { + smb->smb_auxctl |= AUX_BLK; + } memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb, "pm-smbus", 64); } diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c index d029816..ce5ea9e 100644 --- a/hw/i2c/smbus_ich9.c +++ b/hw/i2c/smbus_ich9.c @@ -89,7 +89,7 @@ static void ich9_smbus_realize(PCIDevice *d, Error **errp) pci_set_byte(d->config + ICH9_SMB_HOSTC, 0); /* TODO bar0, bar1: 64bit BAR support*/ - pm_smbus_init(&d->qdev, &s->smb); + pm_smbus_init(&d->qdev, &s->smb, false); pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO, &s->smb.io); } diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index c129985..78b7468 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -370,7 +370,7 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) pci_conf[0x90] = s->smb_io_base | 1; pci_conf[0x91] = s->smb_io_base >> 8; pci_conf[0xd2] = 0x90; - pm_smbus_init(&s->dev.qdev, &s->smb); + pm_smbus_init(&s->dev.qdev, &s->smb, false); memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); apm_init(dev, &s->apm, NULL, s); diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h index cfe596f..471345e 100644 --- a/include/hw/i2c/pm_smbus.h +++ b/include/hw/i2c/pm_smbus.h @@ -33,7 +33,7 @@ typedef struct PMSMBus { bool op_done; } PMSMBus; -void pm_smbus_init(DeviceState *parent, PMSMBus *smb); +void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk); extern const VMStateDescription pmsmb_vmstate;