[v2,1/2] Documentation: devicetree: Add DT bindings to xlnx_vcu driver

Message ID 1512682276-6082-2-git-send-email-dshah@xilinx.com
State Not Applicable
Headers show
Series
  • Documentation and driver of logicoreIP
Related show

Commit Message

Dhaval Shah Dec. 7, 2017, 9:31 p.m.
Add Device Tree binding document for logicoreIP. This logicoreIP
provides the isolation between the processing system and
programmable logic. Also provides the clock related information.

Signed-off-by: Dhaval Shah <dshah@xilinx.com>
---
Changes since v2:
 * Describe the h/w
 * compatible string is updated to make it more specific
   based on the logicoreIP version.
 * Removed that encoder and decoder child nodes and relatd properties as that
   will be a separate driver and dts nodes. other team is working on that.
 * Updated to use as a single driver.

 .../devicetree/bindings/misc/xlnx,vcu.txt          | 31 ++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,vcu.txt

Comments

Rob Herring Dec. 12, 2017, 8:07 p.m. | #1
On Thu, Dec 07, 2017 at 01:31:15PM -0800, Dhaval Shah wrote:
> Add Device Tree binding document for logicoreIP. This logicoreIP
> provides the isolation between the processing system and
> programmable logic. Also provides the clock related information.
> 
> Signed-off-by: Dhaval Shah <dshah@xilinx.com>
> ---
> Changes since v2:
>  * Describe the h/w
>  * compatible string is updated to make it more specific
>    based on the logicoreIP version.
>  * Removed that encoder and decoder child nodes and relatd properties as that
>    will be a separate driver and dts nodes. other team is working on that.
>  * Updated to use as a single driver.
> 
>  .../devicetree/bindings/misc/xlnx,vcu.txt          | 31 ++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/xlnx,vcu.txt

Reviewed-by: Rob Herring <robh@kernel.org>

One nit. Use "dt-bindings: misc: ..." for the subject.
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Dhaval Rajeshbhai Shah Dec. 13, 2017, 5:12 a.m. | #2
Hi Rob,

Thanks a lot for the review.

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Tuesday, December 12, 2017 12:07 PM
> To: Dhaval Rajeshbhai Shah <DSHAH@xilinx.com>
> Cc: arnd@arndb.de; gregkh@linuxfoundation.org;
> pombredanne@nexb.com; mark.rutland@arm.com;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> michal.simek@xilinx.com; Hyun Kwon <hyunk@xilinx.com>; Dhaval
> Rajeshbhai Shah <DSHAH@xilinx.com>
> Subject: Re: [PATCH v2 1/2] Documentation: devicetree: Add DT bindings to
> xlnx_vcu driver
> 
> On Thu, Dec 07, 2017 at 01:31:15PM -0800, Dhaval Shah wrote:
> > Add Device Tree binding document for logicoreIP. This logicoreIP
> > provides the isolation between the processing system and programmable
> > logic. Also provides the clock related information.
> >
> > Signed-off-by: Dhaval Shah <dshah@xilinx.com>
> > ---
> > Changes since v2:
> >  * Describe the h/w
> >  * compatible string is updated to make it more specific
> >    based on the logicoreIP version.
> >  * Removed that encoder and decoder child nodes and relatd properties as
> that
> >    will be a separate driver and dts nodes. other team is working on that.
> >  * Updated to use as a single driver.
> >
> >  .../devicetree/bindings/misc/xlnx,vcu.txt          | 31
> ++++++++++++++++++++++
> >  1 file changed, 31 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/misc/xlnx,vcu.txt
> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> One nit. Use "dt-bindings: misc: ..." for the subject.
I will update subject line and send you v3 patch set.
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Patch

diff --git a/Documentation/devicetree/bindings/misc/xlnx,vcu.txt b/Documentation/devicetree/bindings/misc/xlnx,vcu.txt
new file mode 100644
index 0000000..6786d67
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,vcu.txt
@@ -0,0 +1,31 @@ 
+LogicoreIP designed compatible with Xilinx ZYNQ family.
+-------------------------------------------------------
+
+General concept
+---------------
+
+LogicoreIP design to provide the isolation between processing system
+and programmable logic. Also provides the list of register set to configure
+the frequency.
+
+Required properties:
+- compatible: shall be one of:
+	"xlnx,vcu"
+	"xlnx,vcu-logicoreip-1.0"
+- reg, reg-names: There are two sets of registers need to provide.
+	1. vcu slcr
+	2. Logicore
+	reg-names should contain name for the each register sequence.
+- clocks: phandle for aclk and pll_ref clocksource
+- clock-names: The identification string, "aclk", is always required for
+   the axi clock. "pll_ref" is required for pll.
+Example:
+
+	xlnx_vcu: vcu@a0040000 {
+		compatible = "xlnx,vcu-logicoreip-1.0";
+		reg = <0x0 0xa0040000 0x0 0x1000>,
+			 <0x0 0xa0041000 0x0 0x1000>;
+		reg-names = "vcu_slcr", "logicore";
+		clocks = <&si570_1>, <&clkc 71>;
+		clock-names = "pll_ref", "aclk";
+	};