From patchwork Fri Feb 25 21:27:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 84573 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 03167B70F0 for ; Sat, 26 Feb 2011 08:27:43 +1100 (EST) Received: (qmail 15675 invoked by alias); 25 Feb 2011 21:27:40 -0000 Received: (qmail 15667 invoked by uid 22791); 25 Feb 2011 21:27:39 -0000 X-SWARE-Spam-Status: No, hits=-4.4 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 25 Feb 2011 21:27:35 +0000 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 25 Feb 2011 13:27:33 -0800 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by fmsmga001.fm.intel.com with ESMTP; 25 Feb 2011 13:27:33 -0800 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id 5EF66180949; Fri, 25 Feb 2011 13:27:33 -0800 (PST) Date: Fri, 25 Feb 2011 13:27:33 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Subject: [z32] PATCH: PR target/47715: [x32] TLS doesn't work Message-ID: <20110225212733.GA24182@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, Thread pointer is 32bit in x32 mode. I checked in this patch to properly load thread pointer in x32 mode. H.J. diff --git a/gcc/ChangeLog.x32 b/gcc/ChangeLog.x32 index b1e6753..a7547677 100644 --- a/gcc/ChangeLog.x32 +++ b/gcc/ChangeLog.x32 @@ -1,3 +1,14 @@ +2011-02-25 H.J. Lu + + PR target/47715 + * config/i386/i386.c (get_thread_pointer): Use ptr_mode + instead of Pmode with UNSPEC_TP. + + * config/i386/i386.md (tp_seg): Removed. + (*load_tp_): Replace :P with :PTR. + (*add_tp_): Likewise. + (*load_tp_x32): New. + 2011-02-21 H.J. Lu * config.gcc: Support --enable-ia32 for x86 Linux targets. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index af9f2cd..7b42577 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -12711,7 +12711,9 @@ get_thread_pointer (int to_reg) { rtx tp, reg, insn; - tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP); + tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP); + if (ptr_mode != Pmode) + tp = convert_to_mode (Pmode, tp, 1); if (!to_reg) return tp; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 97986c4..509ee82 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12720,15 +12720,28 @@ (clobber (match_dup 5)) (clobber (reg:CC FLAGS_REG))])]) -;; Segment register for the thread base ptr load -(define_mode_attr tp_seg [(SI "gs") (DI "fs")]) - -;; Load and add the thread base pointer from %gs:0. +;; Load and add the thread base pointer from %gs:0 or %fs:0. (define_insn "*load_tp_" - [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(const_int 0)] UNSPEC_TP))] + [(set (match_operand:PTR 0 "register_operand" "=r") + (unspec:PTR [(const_int 0)] UNSPEC_TP))] "" - "mov{}\t{%%:0, %0|%0, PTR :0}" +{ + if (TARGET_64BIT) + return "mov{}\t{%%fs:0, %0|%0, PTR fs:0}"; + else + return "mov{}\t{%%gs:0, %0|%0, PTR gs:0}"; +} + [(set_attr "type" "imov") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + +(define_insn "*load_tp_x32" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))] + "TARGET_X32" + "mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" [(set_attr "type" "imov") (set_attr "modrm" "0") (set_attr "length" "7") @@ -12736,12 +12749,17 @@ (set_attr "imm_disp" "false")]) (define_insn "*add_tp_" - [(set (match_operand:P 0 "register_operand" "=r") - (plus:P (unspec:P [(const_int 0)] UNSPEC_TP) - (match_operand:P 1 "register_operand" "0"))) + [(set (match_operand:PTR 0 "register_operand" "=r") + (plus:PTR (unspec:PTR [(const_int 0)] UNSPEC_TP) + (match_operand:PTR 1 "register_operand" "0"))) (clobber (reg:CC FLAGS_REG))] "" - "add{}\t{%%:0, %0|%0, PTR :0}" +{ + if (TARGET_64BIT) + return "add{}\t{%%fs:0, %0|%0, PTR fs:0}"; + else + return "add{}\t{%%gs:0, %0|%0, PTR gs:0}"; +} [(set_attr "type" "alu") (set_attr "modrm" "0") (set_attr "length" "7")