From patchwork Thu Dec 7 14:37:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 845606 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PHP1PH8p"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ysynQ42TGz9t34 for ; Fri, 8 Dec 2017 01:40:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1936AC21FAE; Thu, 7 Dec 2017 14:39:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6DD6AC21FE2; Thu, 7 Dec 2017 14:37:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 01389C21F16; Thu, 7 Dec 2017 14:37:39 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id 89DBAC21ED9 for ; Thu, 7 Dec 2017 14:37:30 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id h1so7688348wre.12 for ; Thu, 07 Dec 2017 06:37:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JxCyuXmA+ubc2EgVTxEP70lAOCGoNRGhoXUznr0Laek=; b=PHP1PH8p6W/luHsZN+L/2lKxBPIECi+5kGWk3FSJpJhwG8VLjWsIkgbJphV4NUrK/8 OzXdwPxWfB26pdrZ5re7YygvWoGX/B23hSbOpIo/ipRpI+j6Rw3Ku8Z26HbE6t4y4qhx +5M+D2JeJWbG2V5Udj4Q98tW7wdXQhoUEjk+wEBdtIWyYbU2qj+XnTARCd0d8UJyxwGi m3uOSWRJnYNOYYipQdPL/h2uzGWxDQ3GLIaZmyqyGK3+7t7fkj6TjUknqEgvyT8jdNDT 05MR+pBmM02VX1t4JMMT8G2nPURkSlSUSHvOHUxNP3D4LME3GD1qIoXtIzXd6OZm/ZFy TIxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JxCyuXmA+ubc2EgVTxEP70lAOCGoNRGhoXUznr0Laek=; b=jjPo5W0NDyWDdMyOmbBCAKXefEQuw1pOmQUgyroGk1T8ZKvSwxiimvreZJxPCsLMdU yLkiRgJRLhcEJJ5/dxfCHQMq8OM5y5Lq8pJjqDxQdf0bO9R7fgadcl2Cu6Yz+I5Kv9x9 3zBRskL0dIxMVoWiz+fAihztYFvLjsFEu3lnpihAjY7csSupaW1y7fhiwmc4XQtpr8HE 1h2BCaWl/wp5rzR7qUwZmiALOORKCLviKWQMh7nK3mAM4bRoYIFAAD3EGzOVJzlIlAjQ IjZxuBy/nhwlK2faqxRHtJFDO1wUqLOnlq94DRQOfdkEZGwM6MpX3amsoPg6JM+2lX3T BK5A== X-Gm-Message-State: AJaThX5OOnopGk3jyIoO2k4GMwTF4cbnxIzsRwNRowdyPJqFWVuPMxe2 IlmayTQuSkMH9y4vXOUy5uHWWboQ X-Google-Smtp-Source: AGs4zMYIWBR9gUK5Pf4UGXVS+aZKNAOZ/pMqaa6nbhm80KIiJ5UqXC0cBFRL5BG5pXpd4wj84WoITg== X-Received: by 10.223.173.67 with SMTP id p61mr21134182wrc.226.1512657449827; Thu, 07 Dec 2017 06:37:29 -0800 (PST) Received: from chi.lan (ip-86-49-107-50.net.upcbroadband.cz. [86.49.107.50]) by smtp.gmail.com with ESMTPSA id f18sm5870347wrg.66.2017.12.07.06.37.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Dec 2017 06:37:28 -0800 (PST) From: Marek Vasut X-Google-Original-From: Marek Vasut To: u-boot@lists.denx.de Date: Thu, 7 Dec 2017 15:37:00 +0100 Message-Id: <20171207143712.6434-3-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207143712.6434-1-marek.vasut+renesas@gmail.com> References: <20171207143712.6434-1-marek.vasut+renesas@gmail.com> Cc: Marek Vasut Subject: [U-Boot] [PATCH 03/15] clk: rmobile: Add R8A77970 V3M clock tables X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add clock tables for R8A77970 V3M SoC. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- drivers/clk/renesas/Kconfig | 5 +- drivers/clk/renesas/clk-rcar-gen3.c | 120 +++++++++++++++++++++++++++++++++++- 2 files changed, 121 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 07640d1ccf..8eca88c6ee 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -5,9 +5,8 @@ config CLK_RENESAS Enable support for clock present on Renesas RCar SoCs. config CLK_RCAR_GEN3 - bool "Renesas RCar Gen3 R8A7795/R8A7796 clock driver" + bool "Renesas RCar Gen3 clock driver" def_bool y if RCAR_GEN3 depends on CLK_RENESAS help - Enable this to support the clocks on Renesas RCar Gen3 - R8A7795 and R8A7796 SoC. + Enable this to support the clocks on Renesas RCar Gen3 SoC. diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 4ef35ba47e..c56d52b1ce 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -1,5 +1,5 @@ /* - * Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver + * Renesas RCar Gen3 CPG MSSR driver * * Copyright (C) 2017 Marek Vasut * @@ -20,6 +20,7 @@ #include #include +#include #define CPG_RST_MODEMR 0x0060 @@ -154,6 +155,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_SD, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_R, + CLK_TYPE_GEN3_Z2, }; struct rcar_gen3_cpg_pll_config { @@ -595,6 +597,97 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; +static const struct cpg_core_clk r8a77970_core_clks[] = { + /* External Clock Inputs */ + DEF_INPUT("extal", CLK_EXTAL), + DEF_INPUT("extalr", CLK_EXTALR), + + /* Internal Core Clocks */ + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), + DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), + DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), + + DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), + DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), + DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1), + + /* Core Clock Outputs */ + DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4), + DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), + DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), + DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1), + DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1), + DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1), + DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1), + DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1), + DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1), + DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1), + DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1), + + DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074), + + DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238), + + DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1), + DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1), + + /* NOTE: HDMI, CSI, CAN etc. clock are missing */ + + DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), +}; + +static const struct mssr_mod_clk r8a77970_mod_clks[] = { + DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1), + DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ + DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ + DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ + DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */ + DEF_MOD("msiof3", 208, R8A77970_CLK_MSO), + DEF_MOD("msiof2", 209, R8A77970_CLK_MSO), + DEF_MOD("msiof1", 210, R8A77970_CLK_MSO), + DEF_MOD("msiof0", 211, R8A77970_CLK_MSO), + DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */ + DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("sdif", 314, R8A77970_CLK_SD0), + DEF_MOD("rwdt0", 402, R8A77970_CLK_R), + DEF_MOD("intc-ex", 407, R8A77970_CLK_CP), + DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */ + DEF_MOD("thermal", 522, R8A77970_CLK_CP), + DEF_MOD("pwm", 523, R8A77970_CLK_S2D4), + DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1), + DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1), + DEF_MOD("csi40", 716, R8A77970_CLK_CSI0), + DEF_MOD("du0", 724, R8A77970_CLK_S2D1), + DEF_MOD("lvds", 727, R8A77970_CLK_S2D1), + DEF_MOD("vin3", 808, R8A77970_CLK_S2D1), + DEF_MOD("vin2", 809, R8A77970_CLK_S2D1), + DEF_MOD("vin1", 810, R8A77970_CLK_S2D1), + DEF_MOD("vin0", 811, R8A77970_CLK_S2D1), + DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2), + DEF_MOD("isp", 817, R8A77970_CLK_S2D1), + DEF_MOD("gpio5", 907, R8A77970_CLK_CP), + DEF_MOD("gpio4", 908, R8A77970_CLK_CP), + DEF_MOD("gpio3", 909, R8A77970_CLK_CP), + DEF_MOD("gpio2", 910, R8A77970_CLK_CP), + DEF_MOD("gpio1", 911, R8A77970_CLK_CP), + DEF_MOD("gpio0", 912, R8A77970_CLK_CP), + DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2), + DEF_MOD("rpc", 917, R8A77970_CLK_RPC), + DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2), + DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2), + DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2), + DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2), + DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2), +}; + /* * CPG Clock Data */ @@ -1015,6 +1108,7 @@ static const struct clk_ops gen3_clk_ops = { enum gen3_clk_model { CLK_R8A7795, CLK_R8A7796, + CLK_R8A77970, }; static int gen3_clk_probe(struct udevice *dev) @@ -1050,6 +1144,16 @@ static int gen3_clk_probe(struct udevice *dev) if (ret < 0) return ret; break; + case CLK_R8A77970: + priv->core_clk = r8a77970_core_clks; + priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks); + priv->mod_clk = r8a77970_mod_clks; + priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks); + ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "renesas,r8a77970-rst"); + if (ret < 0) + return ret; + break; default: return -EINVAL; } @@ -1098,6 +1202,15 @@ static struct mstp_stop_table r8a7796_mstp_table[] = { { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, }; +static struct mstp_stop_table r8a77970_mstp_table[] = { + { 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 }, + { 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 }, + { 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 }, + { 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 }, + { 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 }, + { 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 }, +}; + #define TSTR0 0x04 #define TSTR0_STR0 BIT(0) @@ -1117,6 +1230,10 @@ static int gen3_clk_remove(struct udevice *dev) tbl = r8a7796_mstp_table; tbl_size = ARRAY_SIZE(r8a7796_mstp_table); break; + case CLK_R8A77970: + tbl = r8a77970_mstp_table; + tbl_size = ARRAY_SIZE(r8a77970_mstp_table); + break; default: return -EINVAL; } @@ -1136,6 +1253,7 @@ static int gen3_clk_remove(struct udevice *dev) static const struct udevice_id gen3_clk_ids[] = { { .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 }, { .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 }, + { .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 }, { } };