From patchwork Wed Dec 6 05:16:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 845032 X-Patchwork-Delegate: yamada.m@jp.panasonic.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nifty.com header.i=@nifty.com header.b="RJUejzHF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ys6Lx42sbz9s81 for ; Wed, 6 Dec 2017 16:17:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DD303C21ED3; Wed, 6 Dec 2017 05:17:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E05E5C21E22; Wed, 6 Dec 2017 05:16:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C7BBBC21C5D; Wed, 6 Dec 2017 05:16:56 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id 59F38C21C5D for ; Wed, 6 Dec 2017 05:16:55 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id vB65GdxS011389; Wed, 6 Dec 2017 14:16:41 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com vB65GdxS011389 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1512537401; bh=Aoteq4kGnGqHnTtGLhF8l6HmUbS4E92h6a8pRJC7DRU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RJUejzHFeAobHQeAxGFdk+42OQs8vPsmyutrxkpB4PkILwcqgdn/tcaUhKHIhybIK RmIU7WpT0poYVY2dAn82vd67QVFwC0LUCGoAHNOd+6asEF8ZCbV/fo/rWZizyX9JVg SRjc9yqt84+vkLk1MtzYTDc6dr2/TnalpSex/WOxNwKjkN5B7WzAvVeS5i0Ir3gbrr SJiXn7PP0Evf2WS5tEmnqrD3Y2aPHK8CUk11zi+CofID1/znCMmiv32PrDA+rL+Gcf wlrMwAwKij+nF+ILBIGErwEo4DBwB+mxIG80+3p01aJsSZULz+LJ1IUcjeBm5Wpuny Z0qvFWcyckDgQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Wed, 6 Dec 2017 14:16:34 +0900 Message-Id: <1512537394-9608-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512537394-9608-1-git-send-email-yamada.masahiro@socionext.com> References: <1512537394-9608-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 3/3] ARM: uniphier: use FIELD_PREP for PLL settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It is tedious to define both mask and bit-shift. provides a convenient way to get access to register fields with a single shifted mask. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/pll-base-ld20.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c index c9b78b9..385f54d 100644 --- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -19,7 +20,6 @@ #define SC_PLLCTRL_SSC_EN BIT(31) #define SC_PLLCTRL2_NRSTDS BIT(28) #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0) -#define SC_PLLCTRL3_REGI_SHIFT 16 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16) /* PLL type: VPLL27 */ @@ -42,14 +42,16 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, if (freq != UNIPHIER_PLL_FREQ_DEFAULT) { tmp = readl(base); /* SSCPLLCTRL */ tmp &= ~SC_PLLCTRL_SSC_DK_MASK; - tmp |= DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, divn * 512) & - SC_PLLCTRL_SSC_DK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK, + DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, + divn * 512)); writel(tmp, base); tmp = readl(base + 4); tmp &= ~SC_PLLCTRL2_SSC_JK_MASK; - tmp |= DIV_ROUND_CLOSEST(21431887UL * freq, divn * 512) & - SC_PLLCTRL2_SSC_JK_MASK; + tmp |= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK, + DIV_ROUND_CLOSEST(21431887UL * freq, + divn * 512)); writel(tmp, base + 4); udelay(50); @@ -93,7 +95,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) tmp = readl(base + 8); /* SSCPLLCTRL3 */ tmp &= ~SC_PLLCTRL3_REGI_MASK; - tmp |= regi << SC_PLLCTRL3_REGI_SHIFT; + tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi); writel(tmp, base + 8); iounmap(base);