[2/2] target/sh4: add missing tcg_temp_free() in _decode_opc()

Message ID 20171205170013.22337-3-f4bug@amsat.org
State New
Headers show
Series
  • target/sh4: add missing tcg_temp_free()
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Commit Message

Philippe Mathieu-Daudé Dec. 5, 2017, 5 p.m.
missed in c55497ecb8c and 852d481faf7.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/sh4/translate.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Aurelien Jarno Dec. 6, 2017, 9:59 p.m. | #1
On 2017-12-05 14:00, Philippe Mathieu-Daudé wrote:
> missed in c55497ecb8c and 852d481faf7.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/sh4/translate.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 5aeaabdd8d..62d01227fc 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -604,6 +604,7 @@ static void _decode_opc(DisasContext * ctx)
>  	    tcg_gen_subi_i32(addr, REG(B11_8), 4);
>              tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
>  	    tcg_gen_mov_i32(REG(B11_8), addr);
> +        tcg_temp_free(addr);
>  	}
>  	return;
>      case 0x6004:		/* mov.b @Rm+,Rn */
> @@ -1527,6 +1528,7 @@ static void _decode_opc(DisasContext * ctx)
>              tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL);
>              gen_helper_movcal(cpu_env, REG(B11_8), val);
>              tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
> +            tcg_temp_free(val);
>          }
>          ctx->has_movcal = 1;
>  	return;

Good catch!

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

Patch

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 5aeaabdd8d..62d01227fc 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -604,6 +604,7 @@  static void _decode_opc(DisasContext * ctx)
 	    tcg_gen_subi_i32(addr, REG(B11_8), 4);
             tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
 	    tcg_gen_mov_i32(REG(B11_8), addr);
+        tcg_temp_free(addr);
 	}
 	return;
     case 0x6004:		/* mov.b @Rm+,Rn */
@@ -1527,6 +1528,7 @@  static void _decode_opc(DisasContext * ctx)
             tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL);
             gen_helper_movcal(cpu_env, REG(B11_8), val);
             tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
+            tcg_temp_free(val);
         }
         ctx->has_movcal = 1;
 	return;