Patchwork [35/58] vmstate: port pxa2xx_rtc

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Submitter Juan Quintela
Date Feb. 24, 2011, 5:57 p.m.
Message ID <09c4042e275bf04e7082b53fa68d0a72cd87038f.1298569508.git.quintela@redhat.com>
Download mbox | patch
Permalink /patch/84480/
State New
Headers show

Comments

Juan Quintela - Feb. 24, 2011, 5:57 p.m.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
 hw/pxa2xx.c |   85 +++++++++++++++++++++++++---------------------------------
 1 files changed, 37 insertions(+), 48 deletions(-)

Patch

diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 349a5d4..e6542a0 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -1170,62 +1170,53 @@  static void pxa2xx_rtc_init(PXA2xxState *s)
     s->rtc_pi    = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick,    s);
 }

-static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
+static void pxa2xx_rtc_pre_save(void *opaque)
 {
-    PXA2xxState *s = (PXA2xxState *) opaque;
+    PXA2xxState *s = opaque;

     pxa2xx_rtc_hzupdate(s);
     pxa2xx_rtc_piupdate(s);
     pxa2xx_rtc_swupdate(s);
+}

-    qemu_put_be32s(f, &s->rttr);
-    qemu_put_be32s(f, &s->rtsr);
-    qemu_put_be32s(f, &s->rtar);
-    qemu_put_be32s(f, &s->rdar1);
-    qemu_put_be32s(f, &s->rdar2);
-    qemu_put_be32s(f, &s->ryar1);
-    qemu_put_be32s(f, &s->ryar2);
-    qemu_put_be32s(f, &s->swar1);
-    qemu_put_be32s(f, &s->swar2);
-    qemu_put_be32s(f, &s->piar);
-    qemu_put_be32s(f, &s->last_rcnr);
-    qemu_put_be32s(f, &s->last_rdcr);
-    qemu_put_be32s(f, &s->last_rycr);
-    qemu_put_be32s(f, &s->last_swcr);
-    qemu_put_be32s(f, &s->last_rtcpicr);
-    qemu_put_sbe64s(f, &s->last_hz);
-    qemu_put_sbe64s(f, &s->last_sw);
-    qemu_put_sbe64s(f, &s->last_pi);
-}
-
-static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
+static int pxa2xx_rtc_post_load(void *opaque, int version_id)
 {
-    PXA2xxState *s = (PXA2xxState *) opaque;
-
-    qemu_get_be32s(f, &s->rttr);
-    qemu_get_be32s(f, &s->rtsr);
-    qemu_get_be32s(f, &s->rtar);
-    qemu_get_be32s(f, &s->rdar1);
-    qemu_get_be32s(f, &s->rdar2);
-    qemu_get_be32s(f, &s->ryar1);
-    qemu_get_be32s(f, &s->ryar2);
-    qemu_get_be32s(f, &s->swar1);
-    qemu_get_be32s(f, &s->swar2);
-    qemu_get_be32s(f, &s->piar);
-    qemu_get_be32s(f, &s->last_rcnr);
-    qemu_get_be32s(f, &s->last_rdcr);
-    qemu_get_be32s(f, &s->last_rycr);
-    qemu_get_be32s(f, &s->last_swcr);
-    qemu_get_be32s(f, &s->last_rtcpicr);
-    qemu_get_sbe64s(f, &s->last_hz);
-    qemu_get_sbe64s(f, &s->last_sw);
-    qemu_get_sbe64s(f, &s->last_pi);
+    PXA2xxState *s = opaque;

     pxa2xx_rtc_alarm_update(s, s->rtsr);
-
     return 0;
 }

+static const VMStateDescription vmstate_pxa2xx_rtc = {
+    .name = "pxa2xx_rtc",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .minimum_version_id_old = 0,
+    .pre_save = pxa2xx_rtc_pre_save,
+    .post_load = pxa2xx_rtc_post_load,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(rttr, PXA2xxState),
+        VMSTATE_UINT32(rtsr, PXA2xxState),
+        VMSTATE_UINT32(rtar, PXA2xxState),
+        VMSTATE_UINT32(rdar1, PXA2xxState),
+        VMSTATE_UINT32(rdar2, PXA2xxState),
+        VMSTATE_UINT32(ryar1, PXA2xxState),
+        VMSTATE_UINT32(ryar2, PXA2xxState),
+        VMSTATE_UINT32(swar1, PXA2xxState),
+        VMSTATE_UINT32(swar2, PXA2xxState),
+        VMSTATE_UINT32(piar, PXA2xxState),
+        VMSTATE_UINT32(last_rcnr, PXA2xxState),
+        VMSTATE_UINT32(last_rdcr, PXA2xxState),
+        VMSTATE_UINT32(last_rycr, PXA2xxState),
+        VMSTATE_UINT32(last_swcr, PXA2xxState),
+        VMSTATE_UINT32(last_rtcpicr, PXA2xxState),
+        VMSTATE_INT64(last_hz, PXA2xxState),
+        VMSTATE_INT64(last_sw, PXA2xxState),
+        VMSTATE_INT64(last_pi, PXA2xxState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 /* I2C Interface */
 typedef struct {
     i2c_slave i2c;
@@ -2130,8 +2121,7 @@  PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
                     pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
     pxa2xx_rtc_init(s);
-    register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
-                    pxa2xx_rtc_load, s);
+    vmstate_register(NULL, 0, &vmstate_pxa2xx_rtc, s);

     s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
     s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
@@ -2253,8 +2243,7 @@  PXA2xxState *pxa255_init(unsigned int sdram_size)
                     pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
     pxa2xx_rtc_init(s);
-    register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
-                    pxa2xx_rtc_load, s);
+    vmstate_register(NULL, 0, &vmstate_pxa2xx_rtc, s);

     s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
     s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);