From patchwork Tue Dec 5 07:58:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 844639 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yrZ8Z0C1Xz9s7B for ; Tue, 5 Dec 2017 19:06:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A2640C21D78; Tue, 5 Dec 2017 08:02:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 84161C21E77; Tue, 5 Dec 2017 08:00:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 648ECC21EBD; Tue, 5 Dec 2017 07:59:05 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id D68CEC21DED for ; Tue, 5 Dec 2017 07:59:00 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Dec 2017 23:59:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,363,1508828400"; d="scan'208";a="184140420" Received: from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com, ) ([10.226.242.147]) by fmsmga006.fm.intel.com with ESMTP; 04 Dec 2017 23:58:58 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Tue, 5 Dec 2017 15:58:06 +0800 Message-Id: <1512460690-3454-17-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512460690-3454-1-git-send-email-tien.fong.chee@intel.com> References: <1512460690-3454-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Tien Fong , Westergteen Dalon Subject: [U-Boot] [PATCH v5 16/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Enhance preloader header with both additional program length and program entry offset attributes, which offset is relative to the start of program header. Signed-off-by: Tien Fong Chee Reviewed-by: Dinh Nguyen --- arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h index e06b548..b21b871 100644 --- a/arch/arm/mach-socfpga/include/mach/boot0.h +++ b/arch/arm/mach-socfpga/include/mach/boot0.h @@ -12,6 +12,13 @@ .word 0x1337c0d3; /* SoCFPGA preloader validation word */ .word 0xc01df00d; /* Header length(2B),flags(1B),version(1B) */ +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + .word 0xfeedface; /* Program length(4B) */ + .word 0xf00dcafe; /* + * Program entry offset(4B),relative to + * the start of program header + */ +#endif .word 0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */ nop;