[U-Boot] armv8: layerscape: refine port register configuration

Message ID 20171204091305.38048-1-andy.tang@nxp.com
State Superseded
Delegated to: York Sun
Headers show
Series
  • [U-Boot] armv8: layerscape: refine port register configuration
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Commit Message

Yuantian Tang Dec. 4, 2017, 9:13 a.m.
These PP2C and PP3C registers control the configuration of the PHY
control OOB timing for the COMINIT/COMWAKE parameters respectively
for sata port. Overwrite default values with calculated ones to get
better OOB timing.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c        | 6 ++++++
 arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
 2 files changed, 8 insertions(+)

Comments

York Sun Dec. 4, 2017, 4:46 p.m. | #1
On 12/04/2017 01:31 AM, Yuantian Tang wrote:
> These PP2C and PP3C registers control the configuration of the PHY
> control OOB timing for the COMINIT/COMWAKE parameters respectively
> for sata port. Overwrite default values with calculated ones to get
> better OOB timing.
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c        | 6 ++++++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
>  2 files changed, 8 insertions(+)

Andy,

Maybe it was obvious to you, but I couldn't understand why and what you
are changing, except you overwrite two registers.

By the way, you may want to add SATA (in upper case) in the subject.

York
Yuantian Tang Dec. 5, 2017, 1:39 a.m. | #2
Hi York,

This patch is to adjust the OOB (out of bound) timing of sata port. It is totally hardware timing.
I was asked to update those timing by hardware/validation team. They calculated those values from clock frequency. You can apply it safely.

Please apply this patch with SATA added.

Thanks,
Andy

> -----Original Message-----
> From: York Sun
> Sent: Tuesday, December 05, 2017 12:47 AM
> To: Andy Tang <andy.tang@nxp.com>
> Cc: albert.u.boot@aribaud.net; sjg@chromium.org; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8: layerscape: refine port register configuration
> 
> On 12/04/2017 01:31 AM, Yuantian Tang wrote:
> > These PP2C and PP3C registers control the configuration of the PHY
> > control OOB timing for the COMINIT/COMWAKE parameters respectively
> for
> > sata port. Overwrite default values with calculated ones to get better
> > OOB timing.
> >
> > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c        | 6 ++++++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 ++
> >  2 files changed, 8 insertions(+)
> 
> Andy,
> 
> Maybe it was obvious to you, but I couldn't understand why and what you
> are changing, except you overwrite two registers.
> 
> By the way, you may want to add SATA (in upper case) in the subject.
> 
> York
York Sun Dec. 9, 2017, 3:16 a.m. | #3
On 12/04/2017 05:39 PM, Andy Tang wrote:
> Hi York,
> 
> This patch is to adjust the OOB (out of bound) timing of sata port. It is totally hardware timing.
> I was asked to update those timing by hardware/validation team. They calculated those values from clock frequency. You can apply it safely.

Andy, please do not top post. Instead, reply inline with unnecessary
part removed.

Please add details to comments and/or commit message. It will be hard to
maintain the code otherwise.

> 
> Please apply this patch with SATA added.

Please update the subject when you respin this patch.

York

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 497a4b541d..b52653929c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -328,6 +328,8 @@  int sata_init(void)
 #ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 #endif
@@ -335,6 +337,8 @@  int sata_init(void)
 #ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
@@ -355,6 +359,8 @@  int sata_init(void)
 	/* Disable SATA ECC */
 	out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+	out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY2_CFG);
+	out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY3_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 247f09e0f5..664d847e9c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -88,6 +88,8 @@  struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
+#define AHCI_PORT_PHY2_CFG	0x28184d1f
+#define AHCI_PORT_PHY3_CFG	0x0e081509
 #define AHCI_PORT_TRANS_CFG    0x08000029
 #define AHCI_PORT_AXICC_CFG	0x3fffffff