@@ -502,8 +502,8 @@ int arch_early_init_r(void)
* erratum A009635 is valid only for LS2080A SoC and
* its personalitiesi
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A)
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
erratum_a009635();
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
@@ -566,8 +566,8 @@ int timer_init(void)
* For LS2080A SoC and its personalities, timer controller
* offset is different
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A)
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
#endif
@@ -145,7 +145,7 @@ static void fdt_fixup_gic(void *blob)
val = gur_in32(&gur->svr);
- if (SVR_SOC_VER(val) != SVR_LS1043A) {
+ if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
align_64k = 1;
} else if (SVR_REV(val) != REV1_0) {
val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
@@ -327,7 +327,7 @@ static void fdt_fixup_msi(void *blob)
rev = gur_in32(&gur->svr);
- if (SVR_SOC_VER(rev) != SVR_LS1043A)
+ if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
return;
rev = SVR_REV(rev);
@@ -37,9 +37,8 @@ ENTRY(get_gic_offset)
ldr x2, =DCFG_CCSR_SVR
ldr w2, [x2]
rev w2, w2
- mov w3, w2
- ands w3, w3, #SVR_WO_E << 8
- mov w4, #SVR_LS1043A << 8
+ lsr w3, w2, #16
+ ldr w4, =SVR_DEV(SVR_LS1043A)
cmp w3, w4
b.ne 1f
ands w2, w2, #0xff
@@ -92,7 +91,7 @@ ENTRY(lowlevel_init)
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
@@ -224,7 +223,7 @@ ENTRY(lowlevel_init)
*/
bl get_svr
lsr w0, w0, #16
- ldr w1, =SVR_DEV_LS2080A
+ ldr w1, =SVR_DEV(SVR_LS2080A)
cmp w0, w1
b.eq 1f
@@ -76,8 +76,6 @@ struct cpu_type {
#define SVR_LS2081A 0x870918
#define SVR_LS2041A 0x870914
-#define SVR_DEV_LS2080A 0x8701
-
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_REV(svr) (((svr) >> 0) & 0xff)
@@ -85,6 +83,8 @@ struct cpu_type {
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
+#define SVR_DEV(svr) ((svr) >> 8)
+#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
@@ -175,8 +175,8 @@ void qbman_version(u32 *major, u32 *minor)
* LS2080A SoC and its personalities has qbman cotroller version 4.0
* New SoCs like LS2088A, LS1088A has qbman conroller version 4.1
*/
- svr_dev_id = get_svr() >> 16;
- if (svr_dev_id == SVR_DEV_LS2080A) {
+ svr_dev_id = get_svr();
+ if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A))) {
*major = 4;
*minor = 0;
} else {
@@ -198,6 +198,11 @@ bool has_erratum_a010151(void)
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
+#ifdef CONFIG_ARM64
+ if (IS_SVR_DEV(svr, SVR_DEV(SVR_LS1043A)))
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
+#endif
+
switch (soc) {
#ifdef CONFIG_ARM64
case SVR_LS2080A:
@@ -209,8 +214,6 @@ bool has_erratum_a010151(void)
case SVR_LS1046A:
case SVR_LS1012A:
return IS_SVR_REV(svr, 1, 0);
- case SVR_LS1043A:
- return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
#endif
#ifdef CONFIG_ARCH_LS1021A
case SOC_VER_LS1020:
Check LS1043A/LS2080a by device ID without using personality ID to determine revision number. This check applies to all various personalities of the same SoC family. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> --- Changes for v2: Modify the commit message and subject. Add SVR_DEV and IS_SVR_DEV mocros. --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 ++++---- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++-- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 9 ++++----- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 ++-- drivers/net/fsl-mc/dpio/qbman_private.h | 4 ++-- drivers/usb/common/fsl-errata.c | 7 +++++-- 6 files changed, 19 insertions(+), 17 deletions(-)