[OpenWrt-Devel,v2] ARM: dts: Add ethernet PHYs to the a bunch of Geminis

Message ID 20171203150457.21774-1-linus.walleij@linaro.org
State Not Applicable
Delegated to: John Crispin
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  • [OpenWrt-Devel,v2] ARM: dts: Add ethernet PHYs to the a bunch of Geminis
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Commit Message

Linus Walleij Dec. 3, 2017, 3:04 p.m.
These Gemini boards have Ethernet PHY on GPIO bit-banged
MDIO, clearly defined in the corresponding OpenWRT
ethernet patches since ages. Add them in accordance with
the OpenWRT patch so we can use them when we add ethernet
support.

Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Fix the unit names on all PHYs to correspond to the
  actual reg.
---
 arch/arm/boot/dts/gemini-nas4220b.dts | 13 +++++++++++++
 arch/arm/boot/dts/gemini-rut1xx.dts   | 13 +++++++++++++
 arch/arm/boot/dts/gemini-wbd111.dts   | 13 +++++++++++++
 arch/arm/boot/dts/gemini-wbd222.dts   | 18 ++++++++++++++++++
 4 files changed, 57 insertions(+)

Comments

Linus Walleij Dec. 11, 2017, 7:21 a.m. | #1
On Sun, Dec 3, 2017 at 5:06 PM, Andrew Lunn <andrew@lunn.ch> wrote:
> On Sun, Dec 03, 2017 at 04:04:57PM +0100, Linus Walleij wrote:
>> These Gemini boards have Ethernet PHY on GPIO bit-banged
>> MDIO, clearly defined in the corresponding OpenWRT
>> ethernet patches since ages. Add them in accordance with
>> the OpenWRT patch so we can use them when we add ethernet
>> support.
>>
>> Cc: Andrew Lunn <andrew@lunn.ch>
>> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>

Thanks man.

> This is good as is, but i just wonder if the mdio node can be moved
> into the .dtsi file. Four from six have the exact same setup. So i'm
> guessing the reference design has been copied.

Yeah they all have the GPIO lines similarly so far.
I might break out a DTSI with common stuff based on the
reference design. The main DTSI should be the chipset
but we can surely have a gemi-standard-board.dtsi as well.

Yours,
Linus Walleij

Patch

diff --git a/arch/arm/boot/dts/gemini-nas4220b.dts b/arch/arm/boot/dts/gemini-nas4220b.dts
index d6a22e677c7a..943d2d07fac7 100644
--- a/arch/arm/boot/dts/gemini-nas4220b.dts
+++ b/arch/arm/boot/dts/gemini-nas4220b.dts
@@ -64,6 +64,19 @@ 
 		};
 	};
 
+	mdio0: ethernet-phy {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+			<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+			reg = <1>;
+			device_type = "ethernet-phy";
+		};
+	};
+
 	soc {
 		flash@30000000 {
 			status = "okay";
diff --git a/arch/arm/boot/dts/gemini-rut1xx.dts b/arch/arm/boot/dts/gemini-rut1xx.dts
index 500057b6570e..fd55528bba56 100644
--- a/arch/arm/boot/dts/gemini-rut1xx.dts
+++ b/arch/arm/boot/dts/gemini-rut1xx.dts
@@ -58,6 +58,19 @@ 
 		};
 	};
 
+	mdio0: ethernet-phy {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+			<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+			reg = <1>;
+			device_type = "ethernet-phy";
+		};
+	};
+
 	soc {
 		flash@30000000 {
 			status = "okay";
diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts
index b413fd12c5ba..f36e1b65497d 100644
--- a/arch/arm/boot/dts/gemini-wbd111.dts
+++ b/arch/arm/boot/dts/gemini-wbd111.dts
@@ -69,6 +69,19 @@ 
 		};
 	};
 
+	mdio0: ethernet-phy {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+			<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+			reg = <1>;
+			device_type = "ethernet-phy";
+		};
+	};
+
 	soc {
 		flash@30000000 {
 			status = "okay";
diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts
index 3ba710538662..669bd8b5f92f 100644
--- a/arch/arm/boot/dts/gemini-wbd222.dts
+++ b/arch/arm/boot/dts/gemini-wbd222.dts
@@ -69,6 +69,24 @@ 
 		};
 	};
 
+	mdio0: ethernet-phy {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
+			<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+			reg = <1>;
+			device_type = "ethernet-phy";
+		};
+
+		phy1: ethernet-phy@3 {
+			reg = <3>;
+			device_type = "ethernet-phy";
+		};
+	};
+
 	soc {
 		flash@30000000 {
 			status = "okay";