diff mbox series

[v2,3/4] 44x/fsp2: tvsense workaround for dd1

Message ID 20171201155827.57979-3-ivan@de.ibm.com (mailing list archive)
State Accepted
Commit 50f01c57d700cce04a9dc87bc55db2e283f57212
Headers show
Series [v2,1/4] 44x/fsp2: add fsp2 headers | expand

Commit Message

Ivan Mikhaylov Dec. 1, 2017, 3:58 p.m. UTC 
TVSENSE(temperature and voltage sensors) reset is blocked (clock gated)
by the POR default of the TVS sleep config bit. As a consequence,
TVSENSE will provide erratic sensor values, which may result in
spurious (parity) errors recorded in the CMU FIR and leading to
erroneous interrupt requests once the CMU interrupt is unmasked.
Purpose of this to set up CMU in working state in any cases even
in case of parity errors.

Reviewed-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com>
---
 arch/powerpc/platforms/44x/fsp2.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)
diff mbox series

Patch

diff --git a/arch/powerpc/platforms/44x/fsp2.c b/arch/powerpc/platforms/44x/fsp2.c
index baed409..7c9bc93 100644
--- a/arch/powerpc/platforms/44x/fsp2.c
+++ b/arch/powerpc/platforms/44x/fsp2.c
@@ -59,6 +59,23 @@  static int __init fsp2_probe(void)
 	mtdcr(DCRN_PLB6_HD, 0xffff0000);
 	mtdcr(DCRN_PLB6_SHD, 0xffff0000);
 
+	/* TVSENSE reset is blocked (clock gated) by the POR default of the TVS
+	 * sleep config bit. As a consequence, TVSENSE will provide erratic
+	 * sensor values, which may result in spurious (parity) errors
+	 * recorded in the CMU FIR and leading to erroneous interrupt requests
+	 * once the CMU interrupt is unmasked.
+	 */
+
+	/* 1. set TVS1[UNDOZE] */
+	val = mfcmu(CMUN_TVS1);
+	val |= 0x4;
+	mtcmu(CMUN_TVS1, val);
+
+	/* 2. clear FIR[TVS] and FIR[TVSPAR] */
+	val = mfcmu(CMUN_FIR0);
+	val |= 0x30000000;
+	mtcmu(CMUN_FIR0, val);
+
 	/* L2 machine checks */
 	mtl2(L2PLBMCKEN0, 0xffffffff);
 	mtl2(L2PLBMCKEN1, 0x0000ffff);