From patchwork Tue Nov 28 14:17:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Subrahmanya Lingappa X-Patchwork-Id: 842175 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mobiveil.co.in header.i=@mobiveil.co.in header.b="DqAkPowy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ymQk314wBz9t2x for ; Wed, 29 Nov 2017 01:18:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752357AbdK1OSA (ORCPT ); Tue, 28 Nov 2017 09:18:00 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:43744 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752034AbdK1OR7 (ORCPT ); Tue, 28 Nov 2017 09:17:59 -0500 Received: by mail-pl0-f67.google.com with SMTP id s23so257040plk.10 for ; Tue, 28 Nov 2017 06:17:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mobiveil.co.in; s=google; h=from:to:cc:subject:date:message-id; bh=6QLLobqCcrpkVIfJAoE4kBEU0+lboDHR6F2ZmKfJPjE=; b=DqAkPowy+goGDYfCOuJmzLv9GzcpRXPO6/ODMy9bF6dJ+bh+gnFGtjm2pTaVm/8HIr X+38r4A30B6DaEavT6psBJyirrerXeu1+NbjDPkDX4/ICbN1bo8gxCjApdfXHqhhnfsa ujm5MJWG6THRran9t7ln09D2fN6oI4EM20AwU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6QLLobqCcrpkVIfJAoE4kBEU0+lboDHR6F2ZmKfJPjE=; b=pLxZs9/3W98GNEj4Vjtp/7ogAxuZmT5alftWrbo8HkbG7AmsQBpbJiizxs32TPU0S+ Yy437Q5Cg/Cqe5wTQKEJEKAMioXtFwi2ZwJqPLbGXJVj05B5wcaEzGl7HJ5BvQZaMSXY eQKjCW550AdtGaX1oj/+m0C01sBzFsqA7QHtBscsFtCLB4/AuEL+B3QwlSJm+zEUndRy RyDUvkkG7i4EZvVy5pAO4bI0F6YQ2bh52Isv53W23M7R1YE03KvD5DZDUarMa9b6+gBR MDr5jTMIRHmRl1CJqDIaw3ktIpeKhSJyoEVEagKr3XVgYrq/x6SotR0Um0TGBH2MfZf/ Jm4Q== X-Gm-Message-State: AJaThX5aEI8hel4Tna8/0VCQjK+jis1deRu3svqU8/vlFUc3mHbgAvHd ALZ0RE9ZnSgvc3nzUz6g/wSxToQK X-Google-Smtp-Source: AGs4zMYciYIttPaBP6DSO9PIso1D8w3i6HlbM4+ViepJgpZIs08OcywsI8r4BqmC1ciQ91/0NcWsiA== X-Received: by 10.84.160.233 with SMTP id v38mr19097114plg.179.1511878678570; Tue, 28 Nov 2017 06:17:58 -0800 (PST) Received: from localhost.localdomain.localdomain ([182.73.65.126]) by smtp.gmail.com with ESMTPSA id w3sm46928148pge.59.2017.11.28.06.17.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 06:17:57 -0800 (PST) From: Subrahmanya Lingappa To: linux-pci@vger.kernel.org, bhelgaas@google.com, lorenzo.pieralisi@arm.com Cc: devicetree@vger.kernel.org, mingkai.hu@nxp.com, peter.newton@nxp.com, minghuan.lian@nxp.com, rajesh.raina@nxp.com, rajan.kapoor@nxp.com, prabhjot.singh@nxp.com, Subrahmanya Lingappa Subject: [PATCH v4 1/2] PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver DT bindings Date: Tue, 28 Nov 2017 09:17:28 -0500 Message-Id: <1511878648-8188-1-git-send-email-l.subrahmanya@mobiveil.co.in> X-Mailer: git-send-email 1.8.3.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch adds the DT bindings for Mobiveil PCIe Host Bridge IP driver and updates the vendor prefixes file. Signed-off-by: Subrahmanya Lingappa Cc: bhelgaas@google.com Cc: lorenzo.pieralisi@arm.com Cc: linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Rob Herring --- Fixes: - used git mailer, as tabs were converted to spaces by thunderbird before - moved the entry to corrrect alphabetical order in vendor-prefixes.txt - DT binding file was modified to take care of v3 review comments .../devicetree/bindings/pci/mobiveil-pcie.txt | 73 ++++++++++++++++++++++ .../devicetree/bindings/vendor-prefixes.txt | 1 + 2 files changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/mobiveil-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt new file mode 100644 index 0000000..9f3160d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt @@ -0,0 +1,73 @@ +* Mobiveil AXI PCIe Root Port Bridge DT description + +Mobiveil's GPEX 4.0 is PCIe gen4 a root port bridge IP. This configurable IP +has upto 8 outbound and inbound windows for the address translation. + +Required properties: +- #address-cells: Address representation for root ports, set to <3> +- #size-cells: Size representation for root ports, set to <2> +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain "mbvl,gpex40-pcie" +- reg: Should contain PCIe registers location and length + "config_axi_slave": PCIe controller registers + "csr_axi_slave" : Bridge config registers + "gpio_slave" : GPIO registers to control slot power + "apb_csr" : MSI registers + +- device_type: must be "pci" +- apio-wins : number of requested apio outbound windows + default 2 outbound windows are configured - + 1. Config window + 2. Memory window +- ppio-wins : number of requested ppio inbound windows + default 1 inbound memory window is configured. +- bus-range: PCI bus numbers covered +- interrupt-controller: identifies the node as an interrupt controller +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- interrupt-parent : phandle to the interrupt controller that + it is attached to, it should be set to gic to point to + ARM's Generic Interrupt Controller node in system DT. +- interrupts: The interrupt line of the PCIe controller + last cell of this fild is set to 4 to + denote it as IRQ_TYPE_LEVEL_HIGH type interrupt. +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + + +Example: +++++++++ + pcie0: pcie@a0000000 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "mbvl,gpex40-pcie"; + reg = <0xa0000000 0x00001000>, + <0xb0000000 0x00010000>, + <0xff000000 0x00200000>, + <0xb0010000 0x00001000>; + reg-names = "config_axi_slave", + "csr_axi_slave", + "gpio_slave", + "apb_csr"; + device_type = "pci"; + apio-wins = <2>; + ppio-wins = <1>; + bus-range = <0x00000000 0x000000ff>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + interrupts = < 0 89 4 >; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pci_express 1>, + <0 0 0 2 &pci_express 2>, + <0 0 0 3 &pci_express 3>, + <0 0 0 4 &pci_express 4>; + ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; + + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 0994bdd..8263cc7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -197,6 +197,7 @@ lwn Liebherr-Werk Nenzing GmbH macnica Macnica Americas marvell Marvell Technology Group Ltd. maxim Maxim Integrated Products +mbvl Mobiveil Inc. mcube mCube meas Measurement Specialties mediatek MediaTek Inc.