From patchwork Tue Nov 28 10:18:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhishek Goel X-Patchwork-Id: 842055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ymKSX11Pfz9t9S for ; Tue, 28 Nov 2017 21:21:00 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ymKSW40fMzDrM5 for ; Tue, 28 Nov 2017 21:20:59 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=huntbag@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ymKRV6mKNzDrKB for ; Tue, 28 Nov 2017 21:20:05 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vASAJUYG032958 for ; Tue, 28 Nov 2017 05:20:02 -0500 Received: from e06smtp14.uk.ibm.com (e06smtp14.uk.ibm.com [195.75.94.110]) by mx0a-001b2d01.pphosted.com with ESMTP id 2eh2sa8d23-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 28 Nov 2017 05:20:02 -0500 Received: from localhost by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 28 Nov 2017 10:20:00 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp14.uk.ibm.com (192.168.101.144) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Tue, 28 Nov 2017 10:19:57 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vASAJvmZ28246126; Tue, 28 Nov 2017 10:19:57 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 388B011C052; Tue, 28 Nov 2017 10:14:32 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8EBC511C050; Tue, 28 Nov 2017 10:14:31 +0000 (GMT) Received: from fir03.in.ibm.com (unknown [9.124.102.72]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 28 Nov 2017 10:14:31 +0000 (GMT) From: Abhishek Goel To: skiboot@lists.ozlabs.org, stewart@linux.vnet.ibm.com Date: Tue, 28 Nov 2017 15:48:46 +0530 X-Mailer: git-send-email 2.9.3 X-TM-AS-GCONF: 00 x-cbid: 17112810-0016-0000-0000-000005065317 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17112810-0017-0000-0000-00002842364F Message-Id: <20171128101846.6376-1-huntbag@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-28_06:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711280139 Subject: [Skiboot] [PATCH v2] power-mgmt : occ : Add 'freq-domain-indicator' DT property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Add a new device-tree property freq-domain-indicator to define group of CPUs which would share same frequency. This property has been added under power-mgmt node. It is a bitmask which will have different value depending upon the generation of the processor. Bitwise AND is taken between this bitmask value and PIR of cpu. All the CPUs lying in the same frequency domain will have same result for AND. For example, for POWER8 0xFFF8 indicates core wide frequency domain. Taking AND with the PIR of CPUs will yield us a frequency domain which is core wide distribution as last 3 bits have been masked which represent the threads. For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with the PIR of CPUs will yield us frequency domain which is quad wise distribution as last 4 bits have been masked which represent the cores. Signed-off-by: Abhishek Goel --- doc/device-tree/ibm,opal/power-mgt/occ.rst | 21 +++++++++++++++++++++ hw/occ.c | 12 ++++++++++++ 2 files changed, 33 insertions(+) diff --git a/doc/device-tree/ibm,opal/power-mgt/occ.rst b/doc/device-tree/ibm,opal/power-mgt/occ.rst index d13a62b..4dfcf74 100644 --- a/doc/device-tree/ibm,opal/power-mgt/occ.rst +++ b/doc/device-tree/ibm,opal/power-mgt/occ.rst @@ -37,3 +37,24 @@ ibm,pstate-vcss ibm,pstate-vdds These properties list a voltage-identifier of each of the pstates listed in ibm,pstate-ids for the Vcs and Vdd values used for that pstate in that chip. Each VID is a single byte. + +ibm,opal/power-mgt/ibm,freq-domain-indicator +-------------------------------------------- + +This property is a bitmask which will have different value depending upon +the generation of the processor. Frequency domain would indicate group of +CPUs which would share same frequency. Bitwise AND is taken between this +bitmask value and PIR of cpu. All the CPUs lying in the same frequency +domain will have same result for AND. Thus frequency management can be +done based on frequency-domain. A frequency domain may be a core or a +quad, etc depending upon the generation of the processor. + +For example, for POWER8 0xFFF8 indicates core wide frequency domain. +Taking AND with the PIR of CPUs will yield us a frequency domain which is +core wide distribution as last 3 bits have been masked which represent the +threads. + +For POWER9, 0xFFF0 indicates quad wide frequency domain. Taking AND with +the PIR of CPUs will yield us frequency domain which is quad wise +distribution as last 4 bits have been masked which represent the cores. + diff --git a/hw/occ.c b/hw/occ.c index 8ad0dfe..13fed03 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -47,6 +47,9 @@ #define MAX_OPAL_CMD_DATA_LENGTH 4090 #define MAX_OCC_RSP_DATA_LENGTH 8698 +#define P8_PIR_CORE_MASK 0xFFF8 +#define P9_PIR_QUAD_MASK 0xFFF0 + /** * OCC-OPAL Shared Memory Region * @@ -669,6 +672,15 @@ static bool add_cpu_pstate_properties(int *pstate_nom) dt_add_property_cells(power_mgt, "ibm,pstate-nominal", pnom); dt_add_property_cells(power_mgt, "ibm,pstate-max", pmax); + if (proc_gen == proc_gen_p8) + dt_add_property_cells(power_mgt, "ibm,freq-domain-indicator", + P8_PIR_CORE_MASK); + else if (proc_gen == proc_gen_p9) + dt_add_property_cells(power_mgt, "ibm,freq-domain-indicator", + P9_PIR_QUAD_MASK); + else + prerror("OCC: freq-domain-indicator: Processor is not supported\n"); + free(dt_freq); free(dt_id);