| Message ID | 1511853473-16427-2-git-send-email-kever.yang@rock-chips.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | [U-Boot,1/3] rockchip: rk3036: fix pll config for correct frequency | expand |
> After the MASK MACRO update, we need to update the driver at the same time. > This is a fix to: > 37943aa rockchip: rk3036: clean mask definition for cru reg > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > --- > > arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 15 ++++++--------- > 1 file changed, 6 insertions(+), 9 deletions(-) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> After the MASK MACRO update, we need to update the driver at the same time. > This is a fix to: > 37943aa rockchip: rk3036: clean mask definition for cru reg > > Signed-off-by: Kever Yang <kever.yang@rock-chips.com> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > > arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 15 ++++++--------- > 1 file changed, 6 insertions(+), 9 deletions(-) > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 51b2406..84b7ce2 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -329,29 +329,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv) struct rk3036_pll *pll = &priv->cru->pll[1]; /* pll enter slow-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_SLOW << DPLL_MODE_SHIFT); /* use integer mode */ rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, - PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK, + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | dpll_init_cfg.fbdiv); - rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT | - PLL_REFDIV_MASK << PLL_REFDIV_SHIFT, - (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | - dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, + (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | + dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); /* waiting for pll lock */ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) rockchip_udelay(1); /* PLL enter normal-mode */ - rk_clrsetreg(&priv->cru->cru_mode_con, - DPLL_MODE_MASK << DPLL_MODE_SHIFT, + rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, DPLL_MODE_NORM << DPLL_MODE_SHIFT); }
After the MASK MACRO update, we need to update the driver at the same time. This is a fix to: 37943aa rockchip: rk3036: clean mask definition for cru reg Signed-off-by: Kever Yang <kever.yang@rock-chips.com> --- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-)