From patchwork Mon Nov 27 09:39:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 841530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gQRdVME9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ylhbc2yq5z9sP9 for ; Mon, 27 Nov 2017 20:39:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751555AbdK0Jj4 (ORCPT ); Mon, 27 Nov 2017 04:39:56 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:37635 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751336AbdK0Jjz (ORCPT ); Mon, 27 Nov 2017 04:39:55 -0500 Received: by mail-wm0-f67.google.com with SMTP id v186so33317363wma.2 for ; Mon, 27 Nov 2017 01:39:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+kpsIoD/wrZWVcXDPpB3tmCdzqXSFkwzSNBg0mP4l3A=; b=gQRdVME9f6s+N+3eulatL8AJw1q4JR/ZAq+KLiTmT7M9EAiaiod+ElKC1rbN5U6nQ1 lV2FpwqPpScwn8IHBV3aea36CHy9yeSoZc3x7Q3Z+pXOMQKwnV7VwgOs0AdP7sOmHJqM lIySvHboJDw2iL/0SdVgxo4wjNKlxsfDTKUCnd/IhOkeOVkOvT8a3FrpAhylp+RAuKSY vTbcMfPcE2eN4nhDj9GtyQuKcSgH8zwZUZqt/uzwXiLa7OIvP8iWQnAMGccED++kywF7 WAHTJRtnbE4nAcrUStN7AuawihjEt0fSizsUgyGGIqMtoVe6paiYMUKTxTJSquRHIIvG R+BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+kpsIoD/wrZWVcXDPpB3tmCdzqXSFkwzSNBg0mP4l3A=; b=nHzLBNLQFoEbsEjnLPqRcuSN8k3jk3QRANK8skGVHtJAS/Op2VXo+55HLr9S0E2wBy pyf5q+xHoHTwJGCM7tq3ytUVVNY3iXGtR+hjonreczF4R058GASEUrsxYFsecwyvYTjI rhQnEoqNkW45P2s6KIo9e20smnjrMl9VHfh4noK6tM9Z9j4L0A39ZddLZFmZ4AJd1w5E Iwey8OkpZUI3vFNoVqTMimHGQlcn8Gl01ytjB6nB4ILhl0hWB/GZMjQbjfMPJiykPxRd fvPra+rkuD8gDrJ8SsUpCrU9H30bb3jzVgwHnwyp82Zhy4u5OiPaiUa8WZ1na9rMjGHL uezw== X-Gm-Message-State: AJaThX4KyZ8VPhqn0gFTPtE4kFIHnIk9sUHQcNkq4bqco+Zg1GXf5jWb XKgeDFCydZAyOC26PBDfwQ4= X-Google-Smtp-Source: AGs4zMaE6wsiZ+l7ubaaM6lNI5QD0H40TgKgyT0quVMtAFi8aUJy5Kd4MMjFrsTvn0LTb7Q01Ab7xg== X-Received: by 10.28.48.143 with SMTP id w137mr17046955wmw.3.1511775593725; Mon, 27 Nov 2017 01:39:53 -0800 (PST) Received: from localhost (p200300E41F200F003F65F430A8AE2E44.dip0.t-ipconnect.de. [2003:e4:1f20:f00:3f65:f430:a8ae:2e44]) by smtp.gmail.com with ESMTPSA id p42sm50612300wrb.28.2017.11.27.01.39.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Nov 2017 01:39:53 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Daniel Vetter , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/2] drm/tegra: Sanitize format modifiers Date: Mon, 27 Nov 2017 10:39:48 +0100 Message-Id: <20171127093948.20986-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171127093948.20986-1-thierry.reding@gmail.com> References: <20171127093948.20986-1-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that. - The number space is split into two, reserving 32 bits for some "parameter" which most of the modifiers are not going to have. - Symbolic names for the modifiers are not using the standard DRM_FORMAT_MOD_* prefix, which makes them awkward to use. - The vendor prefix NV is somewhat ambiguous. Fortunately, nobody's started using these modifiers, so we can still fix the above issues. Do so by using the standard prefix. Also, remove TEGRA from the name of those modifiers that exist on NVIDIA GPUs as well. In case of the block linear modifiers, make the "parameter" smaller (4 bits, though only 6 values are valid) and don't let that leak into any of the other modifiers. Finally, also use the more canonical NVIDIA instead of the ambiguous NV prefix. Signed-off-by: Thierry Reding Acked-by: Daniel Vetter --- drivers/gpu/drm/tegra/fb.c | 35 +++++++++++++++++++++++++++++------ include/uapi/drm/drm_fourcc.h | 36 +++++++++++++++++++----------------- 2 files changed, 48 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 80540c1c66dc..406e895d82cc 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -54,17 +54,40 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_fb *fb = to_tegra_fb(framebuffer); uint64_t modifier = fb->base.modifier; - switch (fourcc_mod_tegra_mod(modifier)) { - case NV_FORMAT_MOD_TEGRA_TILED: + switch (modifier) { + case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED: tiling->mode = TEGRA_BO_TILING_MODE_TILED; tiling->value = 0; break; - case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0): tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; - tiling->value = fourcc_mod_tegra_param(modifier); - if (tiling->value > 5) - return -EINVAL; + tiling->value = 0; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 1; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 2; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 3; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 4; + break; + + case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = 5; break; default: diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index a76ed8f9e383..e04613d30a13 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -178,7 +178,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_NONE 0 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02 -#define DRM_FORMAT_MOD_VENDOR_NV 0x03 +#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06 @@ -338,29 +338,17 @@ extern "C" { */ #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4) -/* NVIDIA Tegra frame buffer modifiers */ - -/* - * Some modifiers take parameters, for example the number of vertical GOBs in - * a block. Reserve the lower 32 bits for parameters - */ -#define __fourcc_mod_tegra_mode_shift 32 -#define fourcc_mod_tegra_code(val, params) \ - fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) -#define fourcc_mod_tegra_mod(m) \ - (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -#define fourcc_mod_tegra_param(m) \ - (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) +/* NVIDIA frame buffer modifiers */ /* * Tegra Tiled Layout, used by Tegra 2, 3 and 4. * * Pixels are arranged in simple tiles of 16 x 16 bytes. */ -#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) +#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1) /* - * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 + * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later * * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked * vertically by a power of 2 (1 to 32 GOBs) to form a block. @@ -380,7 +368,21 @@ extern "C" { * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format * in full detail. */ -#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ + fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf)) + +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \ + fourcc_mod_code(NVIDIA, 0x10) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \ + fourcc_mod_code(NVIDIA, 0x11) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \ + fourcc_mod_code(NVIDIA, 0x12) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \ + fourcc_mod_code(NVIDIA, 0x13) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \ + fourcc_mod_code(NVIDIA, 0x14) +#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \ + fourcc_mod_code(NVIDIA, 0x15) /* * Broadcom VC4 "T" format