diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index ab8bbb3..c167f77 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -249,8 +249,18 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
 		if (ctrl & NAND_ALE)
 			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
 
+		/*
+		 * atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN
+		 * If NCE is hooked up to NCS3, we don't need to (and can't)
+		 * explicitly set the state of the NCE pin. Instead, the
+		 * controller asserts it automatically as part of a
+		 * command/data access. Only "CE don't care"-type NAND chips
+		 * can be used in this manner.
+		 */
+#ifdef CONFIG_SYS_NAND_ENABLE_PIN
 		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
 				    !(ctrl & NAND_NCE));
+#endif
 		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}