From patchwork Wed Feb 23 11:28:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot, V2] This patch fix the usage of the "CE don't care"-type NAND chips From: michael X-Patchwork-Id: 84128 Message-Id: <20110223112834.GB985@gandalf.sssup.it> To: u-boot@lists.denx.de Cc: Scott Wood Date: Wed, 23 Feb 2011 12:28:34 +0100 Change since V1: - add a better description Signed-off-by: Michael Trimarchi Cc: Scott Wood --- drivers/mtd/nand/atmel_nand.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index ab8bbb3..c167f77 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -249,8 +249,18 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, if (ctrl & NAND_ALE) IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; + /* + * atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN + * If NCE is hooked up to NCS3, we don't need to (and can't) + * explicitly set the state of the NCE pin. Instead, the + * controller asserts it automatically as part of a + * command/data access. Only "CE don't care"-type NAND chips + * can be used in this manner. + */ +#ifdef CONFIG_SYS_NAND_ENABLE_PIN at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); +#endif this->IO_ADDR_W = (void *) IO_ADDR_W; }