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[U-Boot,v2,3/3] dt-bindings: spi: Add andestech atcspi200 spi binding doc

Message ID 1511419091-330-1-git-send-email-uboot@andestech.com
State Deferred
Delegated to: Andes
Headers show
Series [U-Boot,v2,1/3] spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi | expand

Commit Message

Andes Nov. 23, 2017, 6:38 a.m. UTC 
From: Rick Chen <rick@andestech.com>

Add a document to describe Andestech atcspi200 spi and
binding information.

Signed-off-by: Rick Chen <rick@andestech.com>
---
 doc/device-tree-bindings/spi/spi-atcspi200.txt | 37 ++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/spi-atcspi200.txt
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Patch

diff --git a/doc/device-tree-bindings/spi/spi-atcspi200.txt b/doc/device-tree-bindings/spi/spi-atcspi200.txt
new file mode 100644
index 0000000..9c0630b
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-atcspi200.txt
@@ -0,0 +1,37 @@ 
+Andestech ATCSPI200 SPI controller Device Tree Bindings
+-------------------------------------------------------
+ATCSPI200 is a Serial Peripheral Interface (SPI) controller
+which serves as a SPI master or a SPI slave.
+
+It is often be embedded in AE3XX and AE250 platforms.
+
+Required properties:
+- compatible: has to be "andestech,atcspi200".
+- reg: Base address and size of the controllers memory area.
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: Clock phandles (see clock bindings for details).
+- spi-max-frequency: Maximum SPI clocking speed of device in Hz.
+
+Optional properties:
+- num-cs: Number of chip selects used.
+
+Example:
+
+	spi: spi@f0b00000 {
+		compatible = "andestech,atcspi200";
+		reg = <0xf0b00000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		num-cs = <1>;
+		clocks = <&spiclk>;
+		interrupts = <3 4>;
+		flash@0 {
+			compatible = "spi-flash";
+			spi-max-frequency = <50000000>;
+			reg = <0>;
+			spi-cpol;
+			spi-cpha;
+		};
+	};