| Message ID | 1511256349-5564-1-git-send-email-Bhaskar.Upadhaya@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
| Series | [U-Boot,v2] board: freescale: ls1012a: LS1012A-2G5RDB board support | expand |
Hello Bhaskar Please find feedback below. Regards Poonam > -----Original Message----- > From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Bhaskar > Upadhaya > Sent: Tuesday, November 21, 2017 2:56 PM > To: u-boot@lists.denx.de > Cc: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> > Subject: [U-Boot] [PATCH v2] board: freescale: ls1012a: LS1012A-2G5RDB board > support > > LS1012A-2G5RDB belongs to LS1012A family with features 2.5G SGMII PFE MAC, > SATA, USB 2.0/3.0, WiFi, DDR, eMMC, QuadSPI, UART > > Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> > --- > Changes for V2: > 1. Use existing code base of RDB > 2. Correct Copyrights > > Depends on > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch > work.ozlabs.org%2Fcover%2F823205&data=02%7C01%7Cpoonam.aggrwal%40 > nxp.com%7C26a5cf20927d485c1c5808d530fafe78%7C686ea1d3bc2b4c6fa92cd > 99c5c301635%7C0%7C0%7C636468776941150489&sdata=%2FQByjQRDX%2BT > Q%2FJozhlhF3W2t3hWwinT0J%2F%2F%2FlMj2vSI%3D&reserved=0 > > arch/arm/Kconfig | 11 +++++ > arch/arm/cpu/armv8/Kconfig | 2 +- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/fsl-ls1012a-2g5rdb.dts | 16 +++++++ > board/freescale/ls1012ardb/Kconfig | 18 ++++++++ > board/freescale/ls1012ardb/MAINTAINERS | 7 +++ > board/freescale/ls1012ardb/README | 34 ++++++++++++++ > board/freescale/ls1012ardb/ls1012ardb.c | 4 ++ > configs/ls1012a2g5rdb_qspi_defconfig | 53 +++++++++++++++++++++ > drivers/net/pfe_eth/pfe_eth.c | 11 ++++- > include/configs/ls1012a2g5rdb.h | 81 > +++++++++++++++++++++++++++++++++ > 11 files changed, 236 insertions(+), 2 deletions(-) create mode 100644 > arch/arm/dts/fsl-ls1012a-2g5rdb.dts > create mode 100644 configs/ls1012a2g5rdb_qspi_defconfig > create mode 100644 include/configs/ls1012a2g5rdb.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 94ad805..6816b5b > 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -932,6 +932,17 @@ config TARGET_LS1012ARDB > development platform that supports the QorIQ LS1012A > Layerscape Architecture processor. > > +config TARGET_LS1012A2G5RDB > + bool "Support ls1012a2g5rdb" > + select ARCH_LS1012A > + select ARM64 > + select BOARD_LATE_INIT > + help > + Support for Freescale LS1012A2G5RDB platform. > + The LS1012A 2G5 Reference design board (RDB) is a high-performance > + development platform that supports the QorIQ LS1012A > + Layerscape Architecture processor. > + > config TARGET_LS1012AFRDM > bool "Support ls1012afrdm" > select ARCH_LS1012A > diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index > 12aba9d..3de2706 100644 > --- a/arch/arm/cpu/armv8/Kconfig > +++ b/arch/arm/cpu/armv8/Kconfig > @@ -92,7 +92,7 @@ config PSCI_RESET > !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ > !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ > !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ > - !TARGET_LS2081ARDB && \ > + !TARGET_LS2081ARDB && !TARGET_LS1012A2G5RDB && \ Better place for this TARGET would be with other LS1012A targets, which is after TARGET_LS1012AFRDM > !ARCH_UNIPHIER && !TARGET_S32V234EVB > help > Most armv8 systems have PSCI support enabled in EL3, either through > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index > cd540e9..0311d42 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -201,6 +201,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb > \ > fsl-ls1046a-rdb.dtb \ > fsl-ls1012a-qds.dtb \ > fsl-ls1012a-rdb.dtb \ > + fsl-ls1012a-2g5rdb.dtb \ > fsl-ls1012a-frdm.dtb > > dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb diff --git > a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts > new file mode 100644 > index 0000000..8c7f410 > --- /dev/null > +++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts > @@ -0,0 +1,16 @@ > +/* > + * NXP ls1012a 2G5RDB board device tree source > + * > + * Copyright 2017 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/dts-v1/; > +#include "fsl-ls1012a-rdb.dtsi" > + > +/ { > + chosen { > + stdout-path = &duart0; > + }; > +}; > diff --git a/board/freescale/ls1012ardb/Kconfig > b/board/freescale/ls1012ardb/Kconfig > index 98231f9..d13b08e 100644 > --- a/board/freescale/ls1012ardb/Kconfig > +++ b/board/freescale/ls1012ardb/Kconfig > @@ -15,3 +15,21 @@ config SYS_CONFIG_NAME source > "board/freescale/common/Kconfig" > > endif > + > +if TARGET_LS1012A2G5RDB > + > +config SYS_BOARD > + default "ls1012ardb" > + > +config SYS_VENDOR > + default "freescale" > + > +config SYS_SOC > + default "fsl-layerscape" > + > +config SYS_CONFIG_NAME > + default "ls1012a2g5rdb" > + > +source "board/freescale/common/Kconfig" > + > +endif > diff --git a/board/freescale/ls1012ardb/MAINTAINERS > b/board/freescale/ls1012ardb/MAINTAINERS > index 2cb38e7..a0a0d8d 100644 > --- a/board/freescale/ls1012ardb/MAINTAINERS > +++ b/board/freescale/ls1012ardb/MAINTAINERS > @@ -8,3 +8,10 @@ F: configs/ls1012ardb_qspi_defconfig > M: Sumit Garg <sumit.garg@nxp.com> > S: Maintained > F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig > + > +LS1012A2G5RDB BOARD > +M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> > +S: Maintained > +F: board/freescale/ls1012ardb/ > +F: include/configs/ls1012a2g5rdb.h > +F: configs/ls1012a2g5rdb_qspi_defconfig > diff --git a/board/freescale/ls1012ardb/README > b/board/freescale/ls1012ardb/README > index 453b432..3826ce7 100644 > --- a/board/freescale/ls1012ardb/README > +++ b/board/freescale/ls1012ardb/README > @@ -52,3 +52,37 @@ U-boot | 1MB | 0x4010_0000 > U-boot Env | 1MB | 0x4020_0000 > PPA FIT image | 2MB | 0x4050_0000 > Linux ITB | ~53MB | 0x40A0_0000 > + > +LS1012A2G5RDB board Overview > +----------------------- > + - SERDES Connections, 3 lanes supporting: > + - SGMII, SGMII 2.5 > + - SATA 3.0 > + - DDR Controller > + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 > +GT/s > + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI > +chip-select signals to > + - QSPI NOR flash memory > + - USB 3.0 > + - one high-speed USB 2.0/3.0 port. > + - SDIO WiFi, SPI > + - 2 I2C controllers > + - One SATA onboard connectors > + - UART > + - The LS1012A processor consists of two UART controllers, > + out of which only UART1 is used on 2G5RDB. > + - ARM JTAG support > + > +Booting Options > +--------------- > +a) QSPI Flash 1 > + > +QSPI flash map > +-------------- > +Images | Size |QSPI Flash Address > +------------------------------------------ > +RCW + PBI | 1MB | 0x4000_0000 > +U-boot | 1MB | 0x4010_0000 > +U-boot Env | 1MB | 0x4030_0000 > +PPA FIT image | 2MB | 0x4040_0000 > +Linux ITB | ~53MB | 0x4100_0000 Various parts of code and documentation is re-used from ls1012ardb, so it will be good to explain briefly how this board is different from LS1012ARDB in terms of interfaces/features. > diff --git a/board/freescale/ls1012ardb/ls1012ardb.c > b/board/freescale/ls1012ardb/ls1012ardb.c > index 41283db..89f8adf 100644 > --- a/board/freescale/ls1012ardb/ls1012ardb.c > +++ b/board/freescale/ls1012ardb/ls1012ardb.c > @@ -30,7 +30,11 @@ int checkboard(void) > { > u8 in1; > > +#ifdef CONFIG_TARGET_LS1012ARDB > puts("Board: LS1012ARDB "); > +#else > + puts("Board: LS1012A2G5RDB "); > +#endif > > /* Initialize i2c early for Serial flash bank information */ > i2c_set_bus_num(0); > diff --git a/configs/ls1012a2g5rdb_qspi_defconfig > b/configs/ls1012a2g5rdb_qspi_defconfig > new file mode 100644 > index 0000000..80193b3 > --- /dev/null > +++ b/configs/ls1012a2g5rdb_qspi_defconfig > @@ -0,0 +1,53 @@ > +CONFIG_ARM=y > +CONFIG_TARGET_LS1012A2G5RDB=y > +CONFIG_FSL_LS_PPA=y > +CONFIG_QSPI_AHB_INIT=y > +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" > +# CONFIG_SYS_MALLOC_F is not set > +CONFIG_FIT_VERBOSE=y > +CONFIG_OF_BOARD_SETUP=y > +CONFIG_OF_STDOUT_VIA_ALIAS=y > +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" > +CONFIG_QSPI_BOOT=y > +CONFIG_BOOTDELAY=10 > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 > earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" > +# CONFIG_DISPLAY_BOARDINFO is not set > +CONFIG_HUSH_PARSER=y > +CONFIG_CMD_GREPENV=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_I2C=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_PCI=y Does the board have PCI/e interface? > +CONFIG_CMD_SF=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_DHCP=y > +CONFIG_CMD_MII=y > +CONFIG_CMD_PING=y > +CONFIG_CMD_CACHE=y > +CONFIG_CMD_EXT2=y > +CONFIG_CMD_FAT=y > +CONFIG_OF_CONTROL=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_DM=y > +# CONFIG_BLK is not set > +CONFIG_DM_MMC=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH=y > +CONFIG_NETDEVICES=y > +CONFIG_E1000=y Probably this is also not applicable for this board. > +CONFIG_FSL_PFE=y > +CONFIG_PCI=y Not applicable for this board > +CONFIG_DM_PCI=y Same as above > +CONFIG_DM_PCI_COMPAT=y > +CONFIG_PCIE_LAYERSCAPE=y Same as above > +CONFIG_SYS_NS16550=y > +CONFIG_DM_SPI=y > +CONFIG_FSL_DSPI=y Doe the board support DSPI memory? > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_STORAGE=y > diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index > 4db823f..3b17fda 100644 > --- a/drivers/net/pfe_eth/pfe_eth.c > +++ b/drivers/net/pfe_eth/pfe_eth.c The below changes should be a separate patch (add support of 2.5G SGMII in PFE Ethernet driver) > @@ -383,6 +383,11 @@ static void ls1012a_configure_serdes(struct > ls1012a_eth_dev *priv) > struct mii_dev bus; > int value, sgmii_2500 = 0; > struct gemac_s *gem = priv->gem; > + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; > + unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & > + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; > + > + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; > > if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) > sgmii_2500 = 1; > @@ -402,7 +407,9 @@ static void ls1012a_configure_serdes(struct > ls1012a_eth_dev *priv) > > /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ > value = PHY_SGMII_IF_MODE_SGMII; > - if (!sgmii_2500) > + if (srds_s1 == 0x2208) > + value = 0x8; > + else if (!sgmii_2500) > value |= PHY_SGMII_IF_MODE_AN; > else > value |= PHY_SGMII_IF_MODE_SGMII_GBT; @@ -426,6 +433,8 > @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv) > value = PHY_SGMII_CR_DEF_VAL; > if (!sgmii_2500) > value |= PHY_SGMII_CR_RESET_AN; > + if (srds_s1 == 0x2208) > + value = 0x8140; > ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); } > > diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h > new file mode 100644 index 0000000..8c5104d > --- /dev/null > +++ b/include/configs/ls1012a2g5rdb.h > @@ -0,0 +1,81 @@ > +/* > + * Copyright 2017 NXP > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __LS1012A2G5RDB_H__ > +#define __LS1012A2G5RDB_H__ > + > +#include "ls1012a_common.h" > + CONFIGS should be enabled only for interfaces supported by the LS1012A-2G5RDB board > +/* PFE Ethernet */ > +#ifdef CONFIG_FSL_PFE > +#define EMAC1_PHY_ADDR 0x2 > +#define EMAC2_PHY_ADDR 0x1 > +#define CONFIG_PHYLIB > +#define CONFIG_PHY_REALTEK > +#define CONFIG_PHYLIB_10G > +#define CONFIG_PHY_AQUANTIA > +#endif > + > +/* DDR */ > +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 > +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 > +#define CONFIG_NR_DRAM_BANKS 2 > +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 > +#define CONFIG_CMD_MEMINFO > +#define CONFIG_CMD_MEMTEST > +#define CONFIG_SYS_MEMTEST_START 0x80000000 > +#define CONFIG_SYS_MEMTEST_END 0x9fffffff > + > +/* > + * I2C IO expander > + */ > + > +#define I2C_MUX_IO1_ADDR 0x24 > +#define __SW_BOOT_MASK 0xFC > +#define __SW_BOOT_EMU 0x10 > +#define __SW_BOOT_BANK1 0x00 > +#define __SW_BOOT_BANK2 0x01 > +#define __SW_REV_MASK 0x07 > +#define __SW_REV_A 0xF8 > +#define __SW_REV_B 0xF0 > + > +#define I2C_MUX_IO2_ADDR 0x25 > +#define __PHY_MASK 0xF9 > +#define __PHY_ETH2_MASK 0xFB > +#define __PHY_ETH1_MASK 0xFD > + > +/* MMC */ > +#ifdef CONFIG_MMC > +#define CONFIG_FSL_ESDHC > +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 > +#endif > + > +/* SATA */ > +#define CONFIG_LIBATA > +#define CONFIG_SCSI > +#define CONFIG_SCSI_AHCI > +#define CONFIG_SCSI_AHCI_PLAT > +#define CONFIG_CMD_SCSI > + > +#define CONFIG_SYS_SATA AHCI_BASE_ADDR > + > +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 > +#define CONFIG_SYS_SCSI_MAX_LUN 1 > +#define CONFIG_SYS_SCSI_MAX_DEVICE > (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ > + CONFIG_SYS_SCSI_MAX_LUN) > + > +#define CONFIG_PCIE1 /* PCIE controller 1 */ > + > +#define CONFIG_PCI_SCAN_SHOW > + > +#define CONFIG_CMD_MEMINFO > +#define CONFIG_CMD_MEMTEST > +#define CONFIG_SYS_MEMTEST_START 0x80000000 > +#define CONFIG_SYS_MEMTEST_END 0x9fffffff > + > +#include <asm/fsl_secure_boot.h> > + > +#endif /* __LS1012A2G5RDB_H__ */ > -- > 1.9.1 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.de > nx.de%2Flistinfo%2Fu- > boot&data=02%7C01%7Cpoonam.aggrwal%40nxp.com%7C26a5cf20927d485c1 > c5808d530fafe78%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636 > 468776941150489&sdata=xWQBn7BAebTJWlI%2FSrFRZOerkHCqxr%2BUJnxKuin > TY%2B4%3D&reserved=0
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 94ad805..6816b5b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -932,6 +932,17 @@ config TARGET_LS1012ARDB development platform that supports the QorIQ LS1012A Layerscape Architecture processor. +config TARGET_LS1012A2G5RDB + bool "Support ls1012a2g5rdb" + select ARCH_LS1012A + select ARM64 + select BOARD_LATE_INIT + help + Support for Freescale LS1012A2G5RDB platform. + The LS1012A 2G5 Reference design board (RDB) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. + config TARGET_LS1012AFRDM bool "Support ls1012afrdm" select ARCH_LS1012A diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 12aba9d..3de2706 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -92,7 +92,7 @@ config PSCI_RESET !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ - !TARGET_LS2081ARDB && \ + !TARGET_LS2081ARDB && !TARGET_LS1012A2G5RDB && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cd540e9..0311d42 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -201,6 +201,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ + fsl-ls1012a-2g5rdb.dtb \ fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts new file mode 100644 index 0000000..8c7f410 --- /dev/null +++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts @@ -0,0 +1,16 @@ +/* + * NXP ls1012a 2G5RDB board device tree source + * + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1012a-rdb.dtsi" + +/ { + chosen { + stdout-path = &duart0; + }; +}; diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig index 98231f9..d13b08e 100644 --- a/board/freescale/ls1012ardb/Kconfig +++ b/board/freescale/ls1012ardb/Kconfig @@ -15,3 +15,21 @@ config SYS_CONFIG_NAME source "board/freescale/common/Kconfig" endif + +if TARGET_LS1012A2G5RDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012a2g5rdb" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS index 2cb38e7..a0a0d8d 100644 --- a/board/freescale/ls1012ardb/MAINTAINERS +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -8,3 +8,10 @@ F: configs/ls1012ardb_qspi_defconfig M: Sumit Garg <sumit.garg@nxp.com> S: Maintained F: configs/ls1012ardb_qspi_SECURE_BOOT_defconfig + +LS1012A2G5RDB BOARD +M: Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> +S: Maintained +F: board/freescale/ls1012ardb/ +F: include/configs/ls1012a2g5rdb.h +F: configs/ls1012a2g5rdb_qspi_defconfig diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README index 453b432..3826ce7 100644 --- a/board/freescale/ls1012ardb/README +++ b/board/freescale/ls1012ardb/README @@ -52,3 +52,37 @@ U-boot | 1MB | 0x4010_0000 U-boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 + +LS1012A2G5RDB board Overview +----------------------- + - SERDES Connections, 3 lanes supporting: + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - SDIO WiFi, SPI + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on 2G5RDB. + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4030_0000 +PPA FIT image | 2MB | 0x4040_0000 +Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 41283db..89f8adf 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -30,7 +30,11 @@ int checkboard(void) { u8 in1; +#ifdef CONFIG_TARGET_LS1012ARDB puts("Board: LS1012ARDB "); +#else + puts("Board: LS1012A2G5RDB "); +#endif /* Initialize i2c early for Serial flash bank information */ i2c_set_bus_num(0); diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig new file mode 100644 index 0000000..80193b3 --- /dev/null +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012A2G5RDB=y +CONFIG_FSL_LS_PPA=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-2g5rdb" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_FSL_PFE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index 4db823f..3b17fda 100644 --- a/drivers/net/pfe_eth/pfe_eth.c +++ b/drivers/net/pfe_eth/pfe_eth.c @@ -383,6 +383,11 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv) struct mii_dev bus; int value, sgmii_2500 = 0; struct gemac_s *gem = priv->gem; + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; + + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) sgmii_2500 = 1; @@ -402,7 +407,9 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv) /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ value = PHY_SGMII_IF_MODE_SGMII; - if (!sgmii_2500) + if (srds_s1 == 0x2208) + value = 0x8; + else if (!sgmii_2500) value |= PHY_SGMII_IF_MODE_AN; else value |= PHY_SGMII_IF_MODE_SGMII_GBT; @@ -426,6 +433,8 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv) value = PHY_SGMII_CR_DEF_VAL; if (!sgmii_2500) value |= PHY_SGMII_CR_RESET_AN; + if (srds_s1 == 0x2208) + value = 0x8140; ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value); } diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h new file mode 100644 index 0000000..8c5104d --- /dev/null +++ b/include/configs/ls1012a2g5rdb.h @@ -0,0 +1,81 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1012A2G5RDB_H__ +#define __LS1012A2G5RDB_H__ + +#include "ls1012a_common.h" + +/* PFE Ethernet */ +#ifdef CONFIG_FSL_PFE +#define EMAC1_PHY_ADDR 0x2 +#define EMAC2_PHY_ADDR 0x1 +#define CONFIG_PHYLIB +#define CONFIG_PHY_REALTEK +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_AQUANTIA +#endif + +/* DDR */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +/* + * I2C IO expander + */ + +#define I2C_MUX_IO1_ADDR 0x24 +#define __SW_BOOT_MASK 0xFC +#define __SW_BOOT_EMU 0x10 +#define __SW_BOOT_BANK1 0x00 +#define __SW_BOOT_BANK2 0x01 +#define __SW_REV_MASK 0x07 +#define __SW_REV_A 0xF8 +#define __SW_REV_B 0xF0 + +#define I2C_MUX_IO2_ADDR 0x25 +#define __PHY_MASK 0xF9 +#define __PHY_ETH2_MASK 0xFB +#define __PHY_ETH1_MASK 0xFD + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* SATA */ +#define CONFIG_LIBATA +#define CONFIG_SCSI +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_CMD_SCSI + +#define CONFIG_SYS_SATA AHCI_BASE_ADDR + +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#define CONFIG_PCIE1 /* PCIE controller 1 */ + +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#include <asm/fsl_secure_boot.h> + +#endif /* __LS1012A2G5RDB_H__ */
LS1012A-2G5RDB belongs to LS1012A family with features 2.5G SGMII PFE MAC, SATA, USB 2.0/3.0, WiFi, DDR, eMMC, QuadSPI, UART Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> --- Changes for V2: 1. Use existing code base of RDB 2. Correct Copyrights Depends on https://patchwork.ozlabs.org/cover/823205 arch/arm/Kconfig | 11 +++++ arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1012a-2g5rdb.dts | 16 +++++++ board/freescale/ls1012ardb/Kconfig | 18 ++++++++ board/freescale/ls1012ardb/MAINTAINERS | 7 +++ board/freescale/ls1012ardb/README | 34 ++++++++++++++ board/freescale/ls1012ardb/ls1012ardb.c | 4 ++ configs/ls1012a2g5rdb_qspi_defconfig | 53 +++++++++++++++++++++ drivers/net/pfe_eth/pfe_eth.c | 11 ++++- include/configs/ls1012a2g5rdb.h | 81 +++++++++++++++++++++++++++++++++ 11 files changed, 236 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1012a-2g5rdb.dts create mode 100644 configs/ls1012a2g5rdb_qspi_defconfig create mode 100644 include/configs/ls1012a2g5rdb.h