From patchwork Tue Nov 14 11:23:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Neuling X-Patchwork-Id: 837813 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ybm4H4PJXz9s7C for ; Tue, 14 Nov 2017 22:48:47 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ybm4H3VP5zDsXV for ; Tue, 14 Nov 2017 22:48:47 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yblVk3CNzzDrRk for ; Tue, 14 Nov 2017 22:23:10 +1100 (AEDT) Received: from localhost.localdomain (localhost [127.0.0.1]) by ozlabs.org (Postfix) with ESMTP id 3yblVk1K50z9s7g; Tue, 14 Nov 2017 22:23:10 +1100 (AEDT) Received: by localhost.localdomain (Postfix, from userid 1000) id E685BEEA9EE; Tue, 14 Nov 2017 22:23:09 +1100 (AEDT) From: Michael Neuling To: stewart@linux.vnet.ibm.com Date: Tue, 14 Nov 2017 22:23:03 +1100 Message-Id: <20171114112306.8191-2-mikey@neuling.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171114112306.8191-1-mikey@neuling.org> References: <20171114112306.8191-1-mikey@neuling.org> Subject: [Skiboot] [PATCH v2 2/5] npu2: Refactor BAR setting code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, mikey@neuling.org, Reza Arbab , alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This refactors the BAR setting code to make it clearer and handle a larger range of BAR addresses. This is needed as we are about to move the GPU to a physical address that is currently not supported by this code. This change derives group and chip sections of the BAR from the base address rather than the chip_id now. mem sel is also derived from the base address, rather than assuming 0. No functional change. Signed-off-by: Michael Neuling Reviewed-by: Balbir Singh --- v2: Updated comment based on feedback from Balbir --- hw/npu2.c | 11 ++++++----- include/npu2-regs.h | 3 ++- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/npu2.c b/hw/npu2.c index 773ac07bdf..43dfdcb9b3 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -649,11 +649,12 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) npu2_get_gpu_base(ndev, &base, &size); - /* Base address is in GB */ - base >>= 30; - val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, 0ULL, 4); - val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base); - val = SETFIELD(NPU2_MEM_BAR_GROUP | NPU2_MEM_BAR_CHIP, val, p->chip_id); + NPU2DBG(p, "Setting BAR region dt:%llx\n", base); + val = SETFIELD(NPU2_MEM_BAR_EN, 0ULL, 1); + val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, val, base >> (63-14)); + val = SETFIELD(NPU2_MEM_BAR_GROUP, val, base >> (63-18)); + val = SETFIELD(NPU2_MEM_BAR_CHIP, val, base >> (63-21)); + val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base >> (63-33)); val = SETFIELD(NPU2_MEM_BAR_POISON, val, 1); val = SETFIELD(NPU2_MEM_BAR_GRANULE, val, 0); diff --git a/include/npu2-regs.h b/include/npu2-regs.h index ab046acaf3..ae55661274 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -105,7 +105,8 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_TIMER_CFG 0x018 #define NPU2_GPU0_MEM_BAR 0x020 #define NPU2_GPU1_MEM_BAR 0x028 -#define NPU2_MEM_BAR_SEL_MEM PPC_BITMASK(0,2) +#define NPU2_MEM_BAR_EN PPC_BIT(0) +#define NPU2_MEM_BAR_SEL_MEM PPC_BITMASK(1,2) #define NPU2_MEM_BAR_GROUP PPC_BITMASK(3,6) #define NPU2_MEM_BAR_CHIP PPC_BITMASK(7,9) #define NPU2_MEM_BAR_NODE_ADDR PPC_BITMASK(10,21)