[v2,2/5] npu2: Refactor BAR setting code

Message ID 20171114112306.8191-2-mikey@neuling.org
State Accepted
Headers show
Series
  • [v2,1/5] npu2: Create npu2_write_mcd()
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Commit Message

Michael Neuling Nov. 14, 2017, 11:23 a.m.
This refactors the BAR setting code to make it clearer and handle a
larger range of BAR addresses. This is needed as we are about to move
the GPU to a physical address that is currently not supported by this
code.

This change derives group and chip sections of the BAR from the base
address rather than the chip_id now.  mem sel is also derived from the
base address, rather than assuming 0.

No functional change.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Balbir Singh <bsingharora@gmail.com>
---
v2:
  Updated comment based on feedback from Balbir
---
 hw/npu2.c           | 11 ++++++-----
 include/npu2-regs.h |  3 ++-
 2 files changed, 8 insertions(+), 6 deletions(-)

Patch

diff --git a/hw/npu2.c b/hw/npu2.c
index 773ac07bdf..43dfdcb9b3 100644
--- a/hw/npu2.c
+++ b/hw/npu2.c
@@ -649,11 +649,12 @@  static int npu2_assign_gmb(struct npu2_dev *ndev)
 
 	npu2_get_gpu_base(ndev, &base, &size);
 
-	/* Base address is in GB */
-	base >>= 30;
-	val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, 0ULL, 4);
-	val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base);
-	val = SETFIELD(NPU2_MEM_BAR_GROUP | NPU2_MEM_BAR_CHIP, val, p->chip_id);
+	NPU2DBG(p, "Setting BAR region dt:%llx\n", base);
+	val = SETFIELD(NPU2_MEM_BAR_EN, 0ULL, 1);
+	val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, val, base >> (63-14));
+	val = SETFIELD(NPU2_MEM_BAR_GROUP, val, base >> (63-18));
+	val = SETFIELD(NPU2_MEM_BAR_CHIP, val, base >> (63-21));
+	val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base >> (63-33));
 	val = SETFIELD(NPU2_MEM_BAR_POISON, val, 1);
 	val = SETFIELD(NPU2_MEM_BAR_GRANULE, val, 0);
 
diff --git a/include/npu2-regs.h b/include/npu2-regs.h
index ab046acaf3..ae55661274 100644
--- a/include/npu2-regs.h
+++ b/include/npu2-regs.h
@@ -105,7 +105,8 @@  void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
 #define NPU2_TIMER_CFG				0x018
 #define NPU2_GPU0_MEM_BAR			0x020
 #define NPU2_GPU1_MEM_BAR			0x028
-#define   NPU2_MEM_BAR_SEL_MEM			PPC_BITMASK(0,2)
+#define   NPU2_MEM_BAR_EN			PPC_BIT(0)
+#define   NPU2_MEM_BAR_SEL_MEM			PPC_BITMASK(1,2)
 #define   NPU2_MEM_BAR_GROUP			PPC_BITMASK(3,6)
 #define   NPU2_MEM_BAR_CHIP			PPC_BITMASK(7,9)
 #define   NPU2_MEM_BAR_NODE_ADDR		PPC_BITMASK(10,21)