From patchwork Sun Nov 12 13:17:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 837170 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yZZ8V1lTlz9sRW for ; Mon, 13 Nov 2017 00:18:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751223AbdKLNSR (ORCPT ); Sun, 12 Nov 2017 08:18:17 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1311 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750994AbdKLNSQ (ORCPT ); Sun, 12 Nov 2017 08:18:16 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Sun, 12 Nov 2017 05:18:12 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 12 Nov 2017 05:18:16 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 12 Nov 2017 05:18:16 -0800 Received: from DRHQMAIL112.nvidia.com (10.27.9.29) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sun, 12 Nov 2017 13:18:15 +0000 Received: from DRHQMAIL105.nvidia.com (10.27.9.14) by DRHQMAIL112.nvidia.com (10.27.9.29) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sun, 12 Nov 2017 13:18:08 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sun, 12 Nov 2017 13:18:08 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.45]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 12 Nov 2017 05:18:08 -0800 From: Vidya Sagar To: , CC: , , , , , Subject: [PATCH V3 3/3] PCI: tegra: Enable ASPM-L1 capability advertisement Date: Sun, 12 Nov 2017 18:47:54 +0530 Message-ID: <1510492674-12786-4-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510492674-12786-1-git-send-email-vidyas@nvidia.com> References: <1510492674-12786-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enables advertisement of ASPM-L1 support in capability registers of applicable Tegra chips Signed-off-by: Vidya Sagar --- V2: * no change in this patch V3: * no change in this patch drivers/pci/host/pci-tegra.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 29ee4bb0b7c6..fb61202ee60f 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -250,6 +250,9 @@ #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) +#define RP_VEND_XP1 0xf04 +#define RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT BIT(21) + #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) @@ -351,6 +354,7 @@ struct tegra_pcie_soc { bool RAW_violation_fixup; bool program_deskew_time; bool updateFC_threshold; + bool has_aspm_l1; bool has_aspm_l1ss; bool l1ss_rp_wake_fixup; }; @@ -2214,6 +2218,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_CTL1); value |= RP_VEND_CTL1_ERPT; writel(value, port->base + RP_VEND_CTL1); + + if (port->pcie->soc->has_aspm_l1) { + /* Advertise ASPM-L1 state capability*/ + value = readl(port->base + RP_VEND_XP1); + value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT; + writel(value, port->base + RP_VEND_XP1); + } } static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) @@ -2458,6 +2469,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = false, .has_aspm_l1ss = false, .l1ss_rp_wake_fixup = false, }; @@ -2481,6 +2493,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, .has_aspm_l1ss = false, .l1ss_rp_wake_fixup = false, }; @@ -2503,6 +2516,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .RAW_violation_fixup = true, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, .has_aspm_l1ss = false, .l1ss_rp_wake_fixup = false, }; @@ -2533,6 +2547,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .RAW_violation_fixup = false, .program_deskew_time = true, .updateFC_threshold = true, + .has_aspm_l1 = true, .has_aspm_l1ss = true, .l1ss_rp_wake_fixup = true, }; @@ -2556,6 +2571,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, .has_aspm_l1ss = true, .l1ss_rp_wake_fixup = false, };