From patchwork Sun Nov 12 13:17:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 837167 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yZZ8H4R2tz9sRV for ; Mon, 13 Nov 2017 00:18:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751139AbdKLNSH (ORCPT ); Sun, 12 Nov 2017 08:18:07 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1873 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750994AbdKLNSG (ORCPT ); Sun, 12 Nov 2017 08:18:06 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 12 Nov 2017 05:18:03 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 12 Nov 2017 05:18:33 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 12 Nov 2017 05:18:33 -0800 Received: from DRHQMAIL101.nvidia.com (10.27.9.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sun, 12 Nov 2017 13:18:05 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sun, 12 Nov 2017 13:18:05 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sun, 12 Nov 2017 13:18:05 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.45]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 12 Nov 2017 05:18:05 -0800 From: Vidya Sagar To: , CC: , , , , , Subject: [PATCH V3 2/3] PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2 Date: Sun, 12 Nov 2017 18:47:53 +0530 Message-ID: <1510492674-12786-3-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510492674-12786-1-git-send-email-vidyas@nvidia.com> References: <1510492674-12786-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org sets CLKREQ asserted delay to a higher value to avoid unnecessary wake up from L1.2_ENTRY state for Tegra210 Signed-off-by: Vidya Sagar --- V2: * no change in this patch V3: * no change in this patch drivers/pci/host/pci-tegra.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 6d68f49f152e..29ee4bb0b7c6 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -204,6 +204,8 @@ #define RP_L1_PM_SUBSTATES_1_CTL 0xC04 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK 0x1FFF #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY 0x26 +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK (0x1FF << 13) +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY (0x27 << 13) #define RP_L1_PM_SUBSTATES_2_CTL 0xC08 #define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK 0x1FFF @@ -350,6 +352,7 @@ struct tegra_pcie_soc { bool program_deskew_time; bool updateFC_threshold; bool has_aspm_l1ss; + bool l1ss_rp_wake_fixup; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2290,6 +2293,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) (7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT); writel(value, port->base + RP_L1_PM_SUBSTATES_CTL); + if (soc->l1ss_rp_wake_fixup) { + /* Set CLKREQ asserted delay greater than Power_Off + * time (2us) to avoid RP wakeup in L1.2_ENTRY + */ + value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); + value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK; + value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY; + writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL); + } + /* Following is based on clk_m being 19.2 MHz */ value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK; @@ -2446,6 +2459,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2468,6 +2482,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2489,6 +2504,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2518,6 +2534,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .program_deskew_time = true, .updateFC_threshold = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2540,6 +2557,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .program_deskew_time = false, .updateFC_threshold = false, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = false, }; static const struct of_device_id tegra_pcie_of_match[] = {