| Message ID | 1510227868-31564-1-git-send-email-luis.machado@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [doc] Fix latency in pipeline description example | expand |
On 11/09/2017 03:44 AM, Luis Machado wrote: > Am i missing something or is this example incorrect and this should either > have a latency of 9 (patch attached) or a different resource utilization > description, say, containing "div*6" instead? The numbers are somewhat arbitrary, but you are right that there is an inconsistency here that should be fixed, and it doesn't really matter how we fix it. > 2017-11-09 Luis Machado <luis.machado@linaro.org > > * doc/md.texi (Specifying processor pipeline description): Fix > incorrect latency for the div instruction example. OK. Jim
On 11/10/2017 08:30 PM, Jim Wilson wrote: > On 11/09/2017 03:44 AM, Luis Machado wrote: >> Am i missing something or is this example incorrect and this should >> either >> have a latency of 9 (patch attached) or a different resource utilization >> description, say, containing "div*6" instead? > > The numbers are somewhat arbitrary, but you are right that there is an > inconsistency here that should be fixed, and it doesn't really matter > how we fix it. > >> 2017-11-09 Luis Machado <luis.machado@linaro.org >> >> * doc/md.texi (Specifying processor pipeline description): Fix >> incorrect latency for the div instruction example. > > OK. > > Jim > Thanks. I've checked this in now.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3cb3b9e..34e5daf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-11-09 Luis Machado <luis.machado@linaro.org + + * doc/md.texi (Specifying processor pipeline description): Fix + incorrect latency for the div instruction example. + 2017-11-09 Martin Liska <mliska@suse.cz> PR tree-optimization/82669 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index c4c1138..9806b65 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -9617,7 +9617,7 @@ their result is ready in two cycles. The simple integer insns are issued into the first pipeline unless it is reserved, otherwise they are issued into the second pipeline. Integer division and multiplication insns can be executed only in the second integer -pipeline and their results are ready correspondingly in 8 and 4 +pipeline and their results are ready correspondingly in 9 and 4 cycles. The integer division is not pipelined, i.e.@: the subsequent integer division insn can not be issued until the current division insn finished. Floating point insns are fully pipelined and their @@ -9634,7 +9634,7 @@ incurred. To describe all of this we could specify (define_insn_reservation "mult" 4 (eq_attr "type" "mult") "i1_pipeline, nothing*2, (port0 | port1)") -(define_insn_reservation "div" 8 (eq_attr "type" "div") +(define_insn_reservation "div" 9 (eq_attr "type" "div") "i1_pipeline, div*7, div + (port0 | port1)") (define_insn_reservation "float" 3 (eq_attr "type" "float")