| Message ID | 1510219699-79514-1-git-send-email-david.wu@rock-chips.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | None | expand |
> Spam detection software, running on the system "lists.denx.de", > has identified this incoming email as possible spam. The original > message has been attached to this so you can view it or label > similar future email. If you have any questions, see > @@CONTACT_ADDRESS@@ for details. > > Content preview: The GMAC in the RK3228 once again is identical to the incarnation > in the RK3288 and the RK3399, except for where some of the configuration > and control registers are located in the GRF. This adds the RK3368-specific > logic necessary to reuse this driver. [...] > > Content analysis details: (5.7 points, 5.0 required) > > pts rule name description > ---- ---------------------- -------------------------------------------------- > 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL > [211.157.147.133 listed in psbl.surriel.com] > 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server > [58.22.7.114 listed in dnsbl.sorbs.net] > 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) > [211.157.147.133 listed in bl.mailspike.net] > 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted > The GMAC in the RK3228 once again is identical to the incarnation in > the RK3288 and the RK3399, except for where some of the configuration > and control registers are located in the GRF. > > This adds the RK3368-specific logic necessary to reuse this driver. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > > Changes in v2: > - New patch > > drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 85 insertions(+) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Spam detection software, running on the system "lists.denx.de", > has identified this incoming email as possible spam. The original > message has been attached to this so you can view it or label > similar future email. If you have any questions, see > @@CONTACT_ADDRESS@@ for details. > > Content preview: The GMAC in the RK3228 once again is identical to the incarnation > in the RK3288 and the RK3399, except for where some of the configuration > and control registers are located in the GRF. This adds the RK3368-specific > logic necessary to reuse this driver. [...] > > Content analysis details: (5.7 points, 5.0 required) > > pts rule name description > ---- ---------------------- -------------------------------------------------- > 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL > [211.157.147.133 listed in psbl.surriel.com] > 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server > [58.22.7.114 listed in dnsbl.sorbs.net] > 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) > [211.157.147.133 listed in bl.mailspike.net] > 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted > The GMAC in the RK3228 once again is identical to the incarnation in > the RK3288 and the RK3399, except for where some of the configuration > and control registers are located in the GRF. > > This adds the RK3368-specific logic necessary to reuse this driver. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > > Changes in v2: > - New patch > > drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 85 insertions(+) > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Hi David, Am Donnerstag, 9. November 2017, 17:28:19 CET schrieb David Wu: [stuff that somehow got caught by the spam filter] Shouldn't that code also handle the integrated-phy of the rk3228/rk3229? Right now it looks like this only handles rgmii connected external phys but I guess most tv-boxes based on the rk3229 might use the internal phy to save on components. Heiko
Hi Heiko, Yes, Next plan I want to implement the integrated-phy, because some customers are also consulting this feature, but the current RMII/RGMII of internal/external mac_clk compatible configuration still has a problem, I want to solve this first. 在 2017/12/26 4:45, Heiko Stuebner 写道: > Hi David, > > Am Donnerstag, 9. November 2017, 17:28:19 CET schrieb David Wu: > [stuff that somehow got caught by the spam filter] > > Shouldn't that code also handle the integrated-phy of the rk3228/rk3229? > Right now it looks like this only handles rgmii connected external phys > but I guess most tv-boxes based on the rk3229 might use the internal > phy to save on components. > > > Heiko > > >
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index f24c347..a573740 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -15,6 +15,7 @@ #include <asm/arch/periph.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> +#include <asm/arch/grf_rk322x.h> #include <asm/arch/grf_rk3288.h> #include <asm/arch/grf_rk3328.h> #include <asm/arch/grf_rk3368.h> @@ -61,6 +62,39 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); } +static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk322x_grf *grf; + int clk; + enum { + RK3228_GMAC_CLK_SEL_SHIFT = 8, + RK3228_GMAC_CLK_SEL_MASK = GENMASK(9, 8), + RK3228_GMAC_CLK_SEL_125M = 0 << 8, + RK3228_GMAC_CLK_SEL_25M = 3 << 8, + RK3228_GMAC_CLK_SEL_2_5M = 2 << 8, + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3228_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3228_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3228_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); + + return 0; +} + static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3288_grf *grf; @@ -213,6 +247,50 @@ static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) return 0; } +static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_RMII_MODE_SHIFT = 10, + RK3228_RMII_MODE_MASK = BIT(10), + + RK3228_GMAC_PHY_INTF_SEL_SHIFT = 4, + RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3228_GMAC_PHY_INTF_SEL_RGMII = BIT(4), + + RK3228_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), + RK3228_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3228_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), + + RK3228_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), + RK3228_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3228_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), + }; + enum { + RK3228_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + RK3228_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), + + RK3228_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + RK3228_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3228_RMII_MODE_MASK | + RK3228_GMAC_PHY_INTF_SEL_MASK | + RK3228_RXCLK_DLY_ENA_GMAC_MASK | + RK3228_TXCLK_DLY_ENA_GMAC_MASK, + RK3228_GMAC_PHY_INTF_SEL_RGMII | + RK3228_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3228_TXCLK_DLY_ENA_GMAC_ENABLE); + + rk_clrsetreg(&grf->mac_con[0], + RK3228_CLK_RX_DL_CFG_GMAC_MASK | + RK3228_CLK_TX_DL_CFG_GMAC_MASK, + pdata->rx_delay << RK3228_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3228_CLK_TX_DL_CFG_GMAC_SHIFT); +} + static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3288_grf *grf; @@ -420,6 +498,11 @@ const struct eth_ops gmac_rockchip_eth_ops = { .write_hwaddr = designware_eth_write_hwaddr, }; +const struct rk_gmac_ops rk3228_gmac_ops = { + .fix_mac_speed = rk3228_gmac_fix_mac_speed, + .set_to_rgmii = rk3228_gmac_set_to_rgmii, +}; + const struct rk_gmac_ops rk3288_gmac_ops = { .fix_mac_speed = rk3288_gmac_fix_mac_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii, @@ -446,6 +529,8 @@ const struct rk_gmac_ops rv1108_gmac_ops = { }; static const struct udevice_id rockchip_gmac_ids[] = { + { .compatible = "rockchip,rk3228-gmac", + .data = (ulong)&rk3228_gmac_ops }, { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, { .compatible = "rockchip,rk3328-gmac",
Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: The GMAC in the RK3228 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.133 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.133 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted The GMAC in the RK3228 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: David Wu <david.wu@rock-chips.com> --- Changes in v2: - New patch drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+)