Patchwork [IRA] Fix PR46178

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Submitter Chung-Lin Tang
Date Feb. 18, 2011, 7:28 a.m.
Message ID <4D5E1FB4.1040700@codesourcery.com>
Download mbox | patch
Permalink /patch/83537/
State New
Headers show

Comments

Chung-Lin Tang - Feb. 18, 2011, 7:28 a.m.
Hi,
this patch tries to fix PR46178, which is a series of assert fail ICE
cases when decrementing per-regclass curr_reg_pressure[] in
ira-live.c:dec_register_pressure().

The direct cause of the ICE seems to be that the cover class computed
when indexing ira_hard_regno_cover_class[] in mark_hard_reg_dead(),
and the one obtained through ira_class_translate[] (during the per-BB
initializing of curr_reg_pressure[] in process_bb_node_lives()), are
inconsistent. This causes incorrect tracking of the class register
pressures, causing decrementing to < 0 conditions.

The source of this seems to be: in setup_class_translate(), under
flag_ira_algorithm == IRA_ALGORITHM_PRIORITY, the additional setup code
creates a ira_class_translate[] table based on reg_class_contents[]
which is slightly different than the default, which is more based on the
order of cover classes in ira_reg_class_cover[].

During setup_hard_regno_cover_class(), ira_hard_regno_cover_class[] is
then still set up by iterating across ira_reg_class_cover[], causing the
inconsistency.

This patch resolves this by changing the calculation of
ira_hard_regno_cover_class[] in setup_hard_regno_cover_class() to be
based on ira_class_translate[], which should make things consistent.

Bootstrapped and tested on i686 and x86-64 without regressions (with and
without -fira-algorithm=priority in BOOT_CFLAGS and testsuite options).
 Under -fira-algorithm=priority, the gcc.target/i386/divmod*.c failures
mentioned in the bugzilla PR are also fixed.

Ok for trunk?

Thanks,
Chung-Lin

2011-02-18  Chung-Lin Tang  <cltang@codesourcery.com>

	* ira.c (setup_hard_regno_class): Use ira_class_translate[] to
	compute ira_hard_regno_cover_class[].
Vladimir Makarov - Feb. 18, 2011, 3:18 p.m.
On 02/18/2011 02:28 AM, Chung-Lin Tang wrote:
> Hi,
> this patch tries to fix PR46178, which is a series of assert fail ICE
> cases when decrementing per-regclass curr_reg_pressure[] in
> ira-live.c:dec_register_pressure().
>
> The direct cause of the ICE seems to be that the cover class computed
> when indexing ira_hard_regno_cover_class[] in mark_hard_reg_dead(),
> and the one obtained through ira_class_translate[] (during the per-BB
> initializing of curr_reg_pressure[] in process_bb_node_lives()), are
> inconsistent. This causes incorrect tracking of the class register
> pressures, causing decrementing to<  0 conditions.
>
> The source of this seems to be: in setup_class_translate(), under
> flag_ira_algorithm == IRA_ALGORITHM_PRIORITY, the additional setup code
> creates a ira_class_translate[] table based on reg_class_contents[]
> which is slightly different than the default, which is more based on the
> order of cover classes in ira_reg_class_cover[].
>
> During setup_hard_regno_cover_class(), ira_hard_regno_cover_class[] is
> then still set up by iterating across ira_reg_class_cover[], causing the
> inconsistency.
>
> This patch resolves this by changing the calculation of
> ira_hard_regno_cover_class[] in setup_hard_regno_cover_class() to be
> based on ira_class_translate[], which should make things consistent.
>
> Bootstrapped and tested on i686 and x86-64 without regressions (with and
> without -fira-algorithm=priority in BOOT_CFLAGS and testsuite options).
>   Under -fira-algorithm=priority, the gcc.target/i386/divmod*.c failures
> mentioned in the bugzilla PR are also fixed.
>
> Ok for trunk?
>
>
Yes.  The patch is ok.  Thanks for working on the PR, Chung-Lin.

By the way, the priority algorithm might go away if/when graph coloring 
without cover classes is added to gcc.

Patch

Index: ira.c
===================================================================
--- ira.c	(revision 170267)
+++ ira.c	(working copy)
@@ -1033,22 +1033,14 @@ 
 static void
 setup_hard_regno_cover_class (void)
 {
-  int i, j;
-  enum reg_class cl;
+  int i;
 
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     {
-      ira_hard_regno_cover_class[i] = NO_REGS;
-      for (j = 0; j < ira_reg_class_cover_size; j++)
-	{
-	  cl = ira_reg_class_cover[j];
-	  if (ira_class_hard_reg_index[cl][i] >= 0)
-	    {
-	      ira_hard_regno_cover_class[i] = cl;
-	      break;
-	    }
-	}
-
+      ira_hard_regno_cover_class[i]
+	= (TEST_HARD_REG_BIT (no_unit_alloc_regs, i)
+	   ? NO_REGS
+	   : ira_class_translate[REGNO_REG_CLASS (i)]);
     }
 }