diff mbox series

[U-Boot,30/40] arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon

Message ID d97fdcb071ea195ebdbddceaa0cd0d45a39d2251.1509970359.git.michal.simek@xilinx.com
State Accepted
Commit 5e3c90d238d742c101e0b0e904b2e070f32f3f48
Delegated to: Michal Simek
Headers show
Series zynqmp: arm64: DT changes | expand

Commit Message

Michal Simek Nov. 6, 2017, 12:13 p.m. UTC 
From: Manish Narani <manish.narani@xilinx.com>

This patch sets host quirk2 bit field for No 1.8V supported in case of
1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This
property will ensure the SD runs on High Speed mode.

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 9516c799d5d8..0984077bacf5 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -837,6 +837,8 @@ 
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x870>;
 			power-domains = <&pd_sd0>;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 		};
 
 		sdhci1: sdhci@ff170000 {
@@ -851,6 +853,8 @@ 
 			#stream-id-cells = <1>;
 			iommus = <&smmu 0x871>;
 			power-domains = <&pd_sd1>;
+			nvmem-cells = <&soc_revision>;
+			nvmem-cell-names = "soc_revision";
 		};
 
 		pinctrl0: pinctrl@ff180000 {