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[U-Boot,19/40] arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIe

Message ID c70e6fe3a4e4e11038a2d97d43600506efdf7cd6.1509970359.git.michal.simek@xilinx.com
State Accepted
Commit f811eca9db05fc89fe52141b256231ff94859add
Delegated to: Michal Simek
Headers show
Series zynqmp: arm64: DT changes | expand

Commit Message

Michal Simek Nov. 6, 2017, 12:12 p.m. UTC 
From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>

- Enabling GTR lane-0 to PCIe
- Enabling PCIe node in device tree

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-zcu102-revA.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index fd7d6466711b..df916d0f77d5 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -168,7 +168,7 @@ 
 		gtr_sel0 {
 			gpio-hog;
 			gpios = <0 0>;
-			output-high; /* PCIE = 0, DP = 1 */
+			output-low; /* PCIE = 0, DP = 1 */
 			line-name = "sel0";
 		};
 		gtr_sel1 {
@@ -551,7 +551,7 @@  drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 };
 
 &pcie {
-/*	status = "okay"; */
+	status = "okay";
 };
 
 &qspi {