[U-Boot,11/11] arm64: zynqmp: Wire QSPI boot mode for SPL

Message ID	04b2da491ba37688ce351072a9018ace1caf2e3e.1509969762.git.michal.simek@xilinx.com
State	Superseded
Delegated to:	Michal Simek
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Michal Simek <michal.simek@xilinx.com> To: u-boot@lists.denx.de Date: Mon, 6 Nov 2017 13:02:47 +0100 Message-Id: <04b2da491ba37688ce351072a9018ace1caf2e3e.1509969762.git.michal.simek@xilinx.com> In-Reply-To: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com> References: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com> In-Reply-To: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com> References: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com> Subject: [U-Boot] [PATCH 11/11] arm64: zynqmp: Wire QSPI boot mode for SPL Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	[U-Boot,01/11] arm64: zynqmp: Remove slcr with mio status pin detection \| expand [U-Boot,01/11] arm64: zynqmp: Remove slcr with mio status pin detection [U-Boot,02/11] arm64: zynqmp: mp: Correct the R5 release sequence [U-Boot,03/11] arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU table [U-Boot,04/11] tools: mkimage: Extend mkimage to also include pmufw [U-Boot,05/11] arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP defined [U-Boot,06/11] arm64: zynqmp: Add SD1 level shifter mode to alternative selection [U-Boot,07/11] arm64: zynqmp: Use u32 type instead of uint32_t [U-Boot,08/11] arm64: zynqmp: Add support for CG/EG/EV device detection [U-Boot,09/11] arm64: zynqmp: Add new ID for RFSoC [U-Boot,10/11] arm64: zynqmp: Enable debug uart for zc1751 dc5 [U-Boot,11/11] arm64: zynqmp: Wire QSPI boot mode for SPL

Message ID

04b2da491ba37688ce351072a9018ace1caf2e3e.1509969762.git.michal.simek@xilinx.com

State

Superseded

Delegated to:

Michal Simek

Headers

From: Michal Simek <michal.simek@xilinx.com>
To: u-boot@lists.denx.de
Date: Mon,  6 Nov 2017 13:02:47 +0100
Message-Id: <04b2da491ba37688ce351072a9018ace1caf2e3e.1509969762.git.michal.simek@xilinx.com>
In-Reply-To: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com>
References: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com>
In-Reply-To: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com>
References: <3133b3b4955ec21b2869136e7c13f69cb8c2caee.1509969762.git.michal.simek@xilinx.com>
Subject: [U-Boot] [PATCH 11/11] arm64: zynqmp: Wire QSPI boot mode for SPL
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Content-Type: text/plain; charset="utf-8"
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Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

[U-Boot,01/11] arm64: zynqmp: Remove slcr with mio status pin detection | expand

Commit Message

Michal Simek Nov. 6, 2017, 12:02 p.m. UTC

From: Michal Simek <monstr@monstr.eu>

ZynqMP qspi driver is on the way to mainline

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/zynqmp/spl.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
index 468dc1dc4d54..41b0070a5e1a 100644
--- a/arch/arm/cpu/armv8/zynqmp/spl.c
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -102,6 +102,11 @@  u32 spl_boot_device(void)
 	case SW_SATA_MODE:
 		return BOOT_DEVICE_SATA;
 #endif
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	case QSPI_MODE_24BIT:
+	case QSPI_MODE_32BIT:
+		return BOOT_DEVICE_SPI;
+#endif
 	default:
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;

[U-Boot,11/11] arm64: zynqmp: Wire QSPI boot mode for SPL

Commit Message

Patch