From patchwork Wed Feb 16 20:26:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 83395 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 74548B70FD for ; Thu, 17 Feb 2011 07:27:03 +1100 (EST) Received: (qmail 15905 invoked by alias); 16 Feb 2011 20:27:01 -0000 Received: (qmail 15890 invoked by uid 22791); 16 Feb 2011 20:26:58 -0000 X-SWARE-Spam-Status: No, hits=-1.4 required=5.0 tests=AWL, BAYES_00, NO_DNS_FOR_FROM, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mga14.intel.com (HELO mga14.intel.com) (143.182.124.37) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 16 Feb 2011 20:26:53 +0000 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 16 Feb 2011 12:26:50 -0800 X-ExtLoop1: 1 Received: from gnu-6.sc.intel.com ([10.3.194.135]) by azsmga001.ch.intel.com with ESMTP; 16 Feb 2011 12:26:49 -0800 Received: by gnu-6.sc.intel.com (Postfix, from userid 500) id 24F09180D83; Wed, 16 Feb 2011 12:26:49 -0800 (PST) Date: Wed, 16 Feb 2011 12:26:49 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Subject: [x32] PATCH: PR target/47766: [x32] -fstack-protector doesn't work Message-ID: <20110216202649.GA25571@intel.com> Reply-To: "H.J. Lu" MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, X32 is a 64bit target with 32bit address space. So stack is 32bit, not 64bit. I checked this patch into x32 branch to use ptr_mode for stack protect and split. H.J. --- gcc/ 2011-02-16 H.J. Lu PR target/47766 * config/i386/i386.md (PTR): New. (stack_protect_set: Check TARGET_LP64 instead of TARGET_64BIT. (stack_protect_test): Likewise. (stack_protect_set_): Replace ":P" with ":PTR". (stack_tls_protect_set_): Likewise. (stack_tls_protect_test_): Likewise. * config/i386/linux64.h (TARGET_THREAD_SSP_OFFSET): Support TARGET_X32. (TARGET_THREAD_SPLIT_STACK_OFFSET): Likewise. gcc/testsuite/ 2011-02-16 H.J. Lu PR target/47766 * gcc.target/i386/pr47766.c: New. From 98bd5606713752b7ccb61e5e13360e37416c168f Mon Sep 17 00:00:00 2001 From: H.J. Lu Date: Wed, 16 Feb 2011 09:33:11 -0800 Subject: [PATCH 2/4] Add x32 support to stack protect and split. --- gcc/ChangeLog.x32 | 14 ++++++++++++++ gcc/config/i386/i386.md | 41 ++++++++++++++++++++++++----------------- gcc/config/i386/linux64.h | 7 +++++-- 3 files changed, 43 insertions(+), 19 deletions(-) diff --git a/gcc/ChangeLog.x32 b/gcc/ChangeLog.x32 index 2d1afd8..3a7e980 100644 --- a/gcc/ChangeLog.x32 +++ b/gcc/ChangeLog.x32 @@ -1,3 +1,17 @@ +2011-02-16 H.J. Lu + + PR target/47766 + * config/i386/i386.md (PTR): New. + (stack_protect_set: Check TARGET_LP64 instead of TARGET_64BIT. + (stack_protect_test): Likewise. + (stack_protect_set_): Replace ":P" with ":PTR". + (stack_tls_protect_set_): Likewise. + (stack_tls_protect_test_): Likewise. + + * config/i386/linux64.h (TARGET_THREAD_SSP_OFFSET): Support + TARGET_X32. + (TARGET_THREAD_SPLIT_STACK_OFFSET): Likewise. + 2011-02-15 H.J. Lu PR middle-end/47725 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index cef2c19..3c873ce 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -937,6 +937,12 @@ ;; This mode iterator allows :A to be used for patterns that operate on ;; address-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator A [(SI "TARGET_X32") (DI "!TARGET_X32")]) + +;; This mode iterator allows :PTR to be used for patterns that operate on +;; ptr_mode sized quantities. +(define_mode_iterator PTR + [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")]) + ;; Scheduling descriptions @@ -17958,11 +17964,11 @@ #ifdef TARGET_THREAD_SSP_OFFSET operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET); - insn = (TARGET_64BIT + insn = (TARGET_LP64 ? gen_stack_tls_protect_set_di : gen_stack_tls_protect_set_si); #else - insn = (TARGET_64BIT + insn = (TARGET_LP64 ? gen_stack_protect_set_di : gen_stack_protect_set_si); #endif @@ -17972,19 +17978,20 @@ }) (define_insn "stack_protect_set_" - [(set (match_operand:P 0 "memory_operand" "=m") - (unspec:P [(match_operand:P 1 "memory_operand" "m")] UNSPEC_SP_SET)) - (set (match_scratch:P 2 "=&r") (const_int 0)) + [(set (match_operand:PTR 0 "memory_operand" "=m") + (unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")] + UNSPEC_SP_SET)) + (set (match_scratch:PTR 2 "=&r") (const_int 0)) (clobber (reg:CC FLAGS_REG))] "" "mov{}\t{%1, %2|%2, %1}\;mov{}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2" [(set_attr "type" "multi")]) (define_insn "stack_tls_protect_set_" - [(set (match_operand:P 0 "memory_operand" "=m") - (unspec:P [(match_operand:P 1 "const_int_operand" "i")] - UNSPEC_SP_TLS_SET)) - (set (match_scratch:P 2 "=&r") (const_int 0)) + [(set (match_operand:PTR 0 "memory_operand" "=m") + (unspec:PTR [(match_operand:PTR 1 "const_int_operand" "i")] + UNSPEC_SP_TLS_SET)) + (set (match_scratch:PTR 2 "=&r") (const_int 0)) (clobber (reg:CC FLAGS_REG))] "" "mov{}\t{%@:%P1, %2|%2, PTR %@:%P1}\;mov{}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2" @@ -18002,11 +18009,11 @@ #ifdef TARGET_THREAD_SSP_OFFSET operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET); - insn = (TARGET_64BIT + insn = (TARGET_LP64 ? gen_stack_tls_protect_test_di : gen_stack_tls_protect_test_si); #else - insn = (TARGET_64BIT + insn = (TARGET_LP64 ? gen_stack_protect_test_di : gen_stack_protect_test_si); #endif @@ -18020,20 +18027,20 @@ (define_insn "stack_protect_test_" [(set (match_operand:CCZ 0 "flags_reg_operand" "") - (unspec:CCZ [(match_operand:P 1 "memory_operand" "m") - (match_operand:P 2 "memory_operand" "m")] + (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") + (match_operand:PTR 2 "memory_operand" "m")] UNSPEC_SP_TEST)) - (clobber (match_scratch:P 3 "=&r"))] + (clobber (match_scratch:PTR 3 "=&r"))] "" "mov{}\t{%1, %3|%3, %1}\;xor{}\t{%2, %3|%3, %2}" [(set_attr "type" "multi")]) (define_insn "stack_tls_protect_test_" [(set (match_operand:CCZ 0 "flags_reg_operand" "") - (unspec:CCZ [(match_operand:P 1 "memory_operand" "m") - (match_operand:P 2 "const_int_operand" "i")] + (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") + (match_operand:PTR 2 "const_int_operand" "i")] UNSPEC_SP_TLS_TEST)) - (clobber (match_scratch:P 3 "=r"))] + (clobber (match_scratch:PTR 3 "=r"))] "" "mov{}\t{%1, %3|%3, %1}\;xor{}\t{%@:%P2, %3|%3, PTR %@:%P2}" [(set_attr "type" "multi")]) diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h index b962a64..0855cb7 100644 --- a/gcc/config/i386/linux64.h +++ b/gcc/config/i386/linux64.h @@ -124,10 +124,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #ifdef TARGET_LIBC_PROVIDES_SSP /* i386 glibc provides __stack_chk_guard in %gs:0x14, + x32 glibc provides it in %fs:0x18. x86_64 glibc provides it in %fs:0x28. */ -#define TARGET_THREAD_SSP_OFFSET (TARGET_64BIT ? 0x28 : 0x14) +#define TARGET_THREAD_SSP_OFFSET \ + (TARGET_64BIT ? (TARGET_X32 ? 0x18 : 0x28) : 0x14) /* We steal the last transactional memory word. */ #define TARGET_CAN_SPLIT_STACK -#define TARGET_THREAD_SPLIT_STACK_OFFSET (TARGET_64BIT ? 0x70 : 0x30) +#define TARGET_THREAD_SPLIT_STACK_OFFSET \ + (TARGET_64BIT ? (TARGET_X32 ? 0x40 : 0x70) : 0x30) #endif