@@ -1,3 +1,17 @@
+2011-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/47766
+ * config/i386/i386.md (PTR): New.
+ (stack_protect_set: Check TARGET_LP64 instead of TARGET_64BIT.
+ (stack_protect_test): Likewise.
+ (stack_protect_set_<mode>): Replace ":P" with ":PTR".
+ (stack_tls_protect_set_<mode>): Likewise.
+ (stack_tls_protect_test_<mode>): Likewise.
+
+ * config/i386/linux64.h (TARGET_THREAD_SSP_OFFSET): Support
+ TARGET_X32.
+ (TARGET_THREAD_SPLIT_STACK_OFFSET): Likewise.
+
2011-02-15 H.J. Lu <hongjiu.lu@intel.com>
PR middle-end/47725
@@ -937,6 +937,12 @@
;; This mode iterator allows :A to be used for patterns that operate on
;; address-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator A [(SI "TARGET_X32") (DI "!TARGET_X32")])
+
+;; This mode iterator allows :PTR to be used for patterns that operate on
+;; ptr_mode sized quantities.
+(define_mode_iterator PTR
+ [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
+
;; Scheduling descriptions
@@ -17958,11 +17964,11 @@
#ifdef TARGET_THREAD_SSP_OFFSET
operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
- insn = (TARGET_64BIT
+ insn = (TARGET_LP64
? gen_stack_tls_protect_set_di
: gen_stack_tls_protect_set_si);
#else
- insn = (TARGET_64BIT
+ insn = (TARGET_LP64
? gen_stack_protect_set_di
: gen_stack_protect_set_si);
#endif
@@ -17972,19 +17978,20 @@
})
(define_insn "stack_protect_set_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=m")
- (unspec:P [(match_operand:P 1 "memory_operand" "m")] UNSPEC_SP_SET))
- (set (match_scratch:P 2 "=&r") (const_int 0))
+ [(set (match_operand:PTR 0 "memory_operand" "=m")
+ (unspec:PTR [(match_operand:PTR 1 "memory_operand" "m")]
+ UNSPEC_SP_SET))
+ (set (match_scratch:PTR 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
""
"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
[(set_attr "type" "multi")])
(define_insn "stack_tls_protect_set_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=m")
- (unspec:P [(match_operand:P 1 "const_int_operand" "i")]
- UNSPEC_SP_TLS_SET))
- (set (match_scratch:P 2 "=&r") (const_int 0))
+ [(set (match_operand:PTR 0 "memory_operand" "=m")
+ (unspec:PTR [(match_operand:PTR 1 "const_int_operand" "i")]
+ UNSPEC_SP_TLS_SET))
+ (set (match_scratch:PTR 2 "=&r") (const_int 0))
(clobber (reg:CC FLAGS_REG))]
""
"mov{<imodesuffix>}\t{%@:%P1, %2|%2, <iptrsize> PTR %@:%P1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
@@ -18002,11 +18009,11 @@
#ifdef TARGET_THREAD_SSP_OFFSET
operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
- insn = (TARGET_64BIT
+ insn = (TARGET_LP64
? gen_stack_tls_protect_test_di
: gen_stack_tls_protect_test_si);
#else
- insn = (TARGET_64BIT
+ insn = (TARGET_LP64
? gen_stack_protect_test_di
: gen_stack_protect_test_si);
#endif
@@ -18020,20 +18027,20 @@
(define_insn "stack_protect_test_<mode>"
[(set (match_operand:CCZ 0 "flags_reg_operand" "")
- (unspec:CCZ [(match_operand:P 1 "memory_operand" "m")
- (match_operand:P 2 "memory_operand" "m")]
+ (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
+ (match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
- (clobber (match_scratch:P 3 "=&r"))]
+ (clobber (match_scratch:PTR 3 "=&r"))]
""
"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
[(set_attr "type" "multi")])
(define_insn "stack_tls_protect_test_<mode>"
[(set (match_operand:CCZ 0 "flags_reg_operand" "")
- (unspec:CCZ [(match_operand:P 1 "memory_operand" "m")
- (match_operand:P 2 "const_int_operand" "i")]
+ (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
+ (match_operand:PTR 2 "const_int_operand" "i")]
UNSPEC_SP_TLS_TEST))
- (clobber (match_scratch:P 3 "=r"))]
+ (clobber (match_scratch:PTR 3 "=r"))]
""
"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%@:%P2, %3|%3, <iptrsize> PTR %@:%P2}"
[(set_attr "type" "multi")])
@@ -124,10 +124,13 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#ifdef TARGET_LIBC_PROVIDES_SSP
/* i386 glibc provides __stack_chk_guard in %gs:0x14,
+ x32 glibc provides it in %fs:0x18.
x86_64 glibc provides it in %fs:0x28. */
-#define TARGET_THREAD_SSP_OFFSET (TARGET_64BIT ? 0x28 : 0x14)
+#define TARGET_THREAD_SSP_OFFSET \
+ (TARGET_64BIT ? (TARGET_X32 ? 0x18 : 0x28) : 0x14)
/* We steal the last transactional memory word. */
#define TARGET_CAN_SPLIT_STACK
-#define TARGET_THREAD_SPLIT_STACK_OFFSET (TARGET_64BIT ? 0x70 : 0x30)
+#define TARGET_THREAD_SPLIT_STACK_OFFSET \
+ (TARGET_64BIT ? (TARGET_X32 ? 0x40 : 0x70) : 0x30)
#endif
Hi, X32 is a 64bit target with 32bit address space. So stack is 32bit, not 64bit. I checked this patch into x32 branch to use ptr_mode for stack protect and split. H.J. --- gcc/ 2011-02-16 H.J. Lu <hongjiu.lu@intel.com> PR target/47766 * config/i386/i386.md (PTR): New. (stack_protect_set: Check TARGET_LP64 instead of TARGET_64BIT. (stack_protect_test): Likewise. (stack_protect_set_<mode>): Replace ":P" with ":PTR". (stack_tls_protect_set_<mode>): Likewise. (stack_tls_protect_test_<mode>): Likewise. * config/i386/linux64.h (TARGET_THREAD_SSP_OFFSET): Support TARGET_X32. (TARGET_THREAD_SPLIT_STACK_OFFSET): Likewise. gcc/testsuite/ 2011-02-16 H.J. Lu <hongjiu.lu@intel.com> PR target/47766 * gcc.target/i386/pr47766.c: New. From 98bd5606713752b7ccb61e5e13360e37416c168f Mon Sep 17 00:00:00 2001 From: H.J. Lu <hjl.tools@gmail.com> Date: Wed, 16 Feb 2011 09:33:11 -0800 Subject: [PATCH 2/4] Add x32 support to stack protect and split. --- gcc/ChangeLog.x32 | 14 ++++++++++++++ gcc/config/i386/i386.md | 41 ++++++++++++++++++++++++----------------- gcc/config/i386/linux64.h | 7 +++++-- 3 files changed, 43 insertions(+), 19 deletions(-)