From patchwork Wed Feb 16 09:05:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joerg Dorchain X-Patchwork-Id: 83346 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D9772B7111 for ; Wed, 16 Feb 2011 20:05:56 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758758Ab1BPJFy (ORCPT ); Wed, 16 Feb 2011 04:05:54 -0500 Received: from RedStar.dorchain.net ([212.88.133.153]:42187 "EHLO Redstar.dorchain.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752579Ab1BPJFv (ORCPT ); Wed, 16 Feb 2011 04:05:51 -0500 Received: from Redstar.dorchain.net (localhost [127.0.0.1]) by Redstar.dorchain.net (8.14.4/8.14.3) with ESMTP id p1G95mYu019751 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 16 Feb 2011 10:05:48 +0100 X-DKIM: OpenDKIM Filter v2.1.3 Redstar.dorchain.net p1G95mYu019751 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=dorchain.net; s=redstar; t=1297847148; bh=+a+a6q6gIr7s7B8rpbnYV4QIIhScu69W1vbmZRufaYE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=Ed2bupp70uDwRtEiq9Fr9rAr2PXGYjBEQcTjDj9XKZuDJEuqlncO6BwOrqg8nb4Jp UUyBmjDk4LK5LrguYslpxwAxgTn7UNiBbtjK5NTLQAptIq7e7anUe2qavA60Ia1/Tp wNFJxEO2U/+WjOgIFcLFCXVpNSVSUGpGYgpq2ye8= Received: (from joerg@localhost) by Redstar.dorchain.net (8.14.4/8.13.8/Submit) id p1G95mNN019749 for linux-ide@vger.kernel.org; Wed, 16 Feb 2011 10:05:48 +0100 Date: Wed, 16 Feb 2011 10:05:48 +0100 From: Joerg Dorchain To: linux-ide@vger.kernel.org Subject: [Patch] enable AHCI mode on certain ich chipsets Message-ID: <20110216090548.GQ5778@Redstar.dorchain.net> MIME-Version: 1.0 Content-Disposition: inline X-message-flag: Please send messages in plain text only. Thanks! X-Bindford: 6200 (more Power!) X-Ray: beware User-Agent: Mutt/1.5.20 (2009-06-14) X-Virus-Scanned: clamav-milter 0.96.5 at Redstar X-Virus-Status: Clean Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org Hello all, this patch allows to force ICH7/8/9 into AHCI mode. This is needed because some BIOSes do not make AHCI-mode operation available to the user. As the Intel documentation states that the OS should not carry out the operation - the user must force this on the kernel commandline using quirk_ich_force_ahci As this quirk gets called whilst the PCI subsystem is walking the PCI bus, we declare this quirk against the LPC (device 00:1f.0), so that we can frob 00:1f.2 before the PCI code has scanned it. Note: the pci id might change due to this (e.g. from 27c4 to 27c5) For working suspend/resume, the next patch is required, too. Bye, Joerg Signed-Off-By: joerg Dorchain --- linux/drivers/pci/quirks.c.orig 2011-02-04 18:29:03.000000000 +0100 +++ linux/drivers/pci/quirks.c 2011-02-12 07:07:57.000000000 +0100 @@ -2684,6 +2684,74 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); /* + * Force ICH7/8/9 into AHCI mode. This is needed because some + * BIOSes do not make AHCI-mode operation available to the user. + * As the Intel documentation states that the OS should not carry + * out the operation - the user must force this on the kernel + * commandline using quirk_ich_force_ahci + * + * As this quirk gets called whilst the PCI subsystem is + * walking the PCI bus, we declare this quirk against the LPC + * (device 00:1f.0), so that we can frob 00:1f.2 before the PCI + * code has scanned it. + * Note: the pci id might change due to this (e.g. from 27c4 to 27c5) + * + */ + +static bool ich_force_ahci_mode; /* defaults to false */ + +static int __init ich789_force_ahci_mode_setup(char *str) +{ + ich_force_ahci_mode = true; + return 0; +} +early_param("quirk_ich_force_ahci", ich789_force_ahci_mode_setup); + +static void ich789_force_ahci_mode(struct pci_dev *pdev) +{ + u8 amrval; + u8 sclkgc; + const int ich89_address_map_reg = 0x90; + const int ich89_sata_clock_gen_config_reg = 0x9c; + + if (!ich_force_ahci_mode) + return; + + /* ICH8 datasheet section 12.1.33 */ + if (!pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), + ich89_address_map_reg, &amrval)) { + + if (amrval & (BIT(6) | BIT(7))) { + dev_printk(KERN_DEBUG, &pdev->dev, + "ICH7/8/9 SATA controller not in IDE mode. Not modifying.\n"); + return; + } + if (amrval & (BIT(0) | BIT(1))) + dev_printk(KERN_DEBUG, &pdev->dev, + "ICH7/8/9 in SATA/PATA combined mode. Untested.\n"); + /* AHCI mode */ + amrval |= BIT(6); + amrval &= ~BIT(7); + pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), + ich89_sata_clock_gen_config_reg, &sclkgc); + dev_printk(KERN_DEBUG, &pdev->dev, "sclkgc is %#0x\n", sclkgc); + pci_bus_write_config_byte(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), + ich89_address_map_reg, amrval); + dev_printk(KERN_DEBUG, &pdev->dev, "Forced ICH7/8/9 mode PIIX->AHCI\n"); + } +} +/* ICH7 */ +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x27b9, ich789_force_ahci_mode); +/* ICH8 */ +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, ich789_force_ahci_mode); +/* ICH9R LPC */ +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2916, ich789_force_ahci_mode); +/* ICH9M LPC */ +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2917, ich789_force_ahci_mode); +/* ICH9M-E LPC */ +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2919, ich789_force_ahci_mode); + +/* * This is a quirk for the Ricoh MMC controller found as a part of * some mulifunction chips.