From patchwork Wed Nov 1 04:04:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 832838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=aj.id.au header.i=@aj.id.au header.b="RdMOLE8i"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="psUZBRNI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yRZQ752Clz9t3r for ; Wed, 1 Nov 2017 15:05:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753393AbdKAEFu (ORCPT ); Wed, 1 Nov 2017 00:05:50 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:44499 "EHLO out4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753145AbdKAEFr (ORCPT ); Wed, 1 Nov 2017 00:05:47 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 583E220AF9; Wed, 1 Nov 2017 00:05:46 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 01 Nov 2017 00:05:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=bFr4nZKuaZM2a1Je9 /6jj05bVXQb0VIVZDUXUld1eSc=; b=RdMOLE8iLheeAD6psn9F6AkHkr0TnN+w0 3P38MToDXWOuzOlXrH57uQvWekJQIZiGdwNmDhbv3+rA5+AAZiiXfNWZC9dWucwM AVG5Ndpm2Sjkx+KFhOHgtxQbhLQPQJIOCuzjvLPP8QJb15TX5iFT1ekazD3GLC3B teXwq+QmTa5HmiQ7mwx7O1vn/TXg7z+IKHbrtsNAX/s8DkloHc43s10WuvanbM3O skr3Bh4Tl78l1oX750pZ4sBznjHLVVMcBR2UugRiPN1b8V04YLdscvOOLTAZ62bw j6tfgOcBYcxWemwRR3Ir1uHRXFyJwo8jEngGHp8O3An+2h4iLjjDA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=bFr4nZKuaZM2a1Je9/6jj05bVXQb0VIVZDUXUld1eSc=; b=psUZBRNI nid3MsoBse6MPsE+WN75J4TZpVoHoWaaHM/Pxlg0lz74Gjpvy7xxb7rxxL3dwrU0 4MFwv0F/PHOu4jVujzEVegxmM6anDONV929FYFClJVQHR5D/wRyvPt0+G0Llpmby rKcMfGDqaJYvigM5EhDD941HeehQKG5oaI+06yjgtB1PlkI4evs/XRFNj32+q60z k/KSwKg3wf9UhA86UqQ7X32ooiIHTjuyI9eJf1TzB4UM2PxQTwyR/xAqUQWa9THd QQuf+29Jx4JvxI3g7RVXfJLVD+ytklgWP1gcTQMUgLls+OA19H6ApPxMk8luWqiV 0ybythA8DVTAOw== X-ME-Sender: Received: from keelia.au.ibm.com (unknown [122.99.82.10]) by mail.messagingengine.com (Postfix) with ESMTPA id 5561D7F96B; Wed, 1 Nov 2017 00:05:42 -0400 (EDT) From: Andrew Jeffery To: linux-gpio@vger.kernel.org Cc: Andrew Jeffery , linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, frowand.list@gmail.com, joel@jms.id.au, ckeepax@opensource.wolfsonmicro.com, ldewangan@nvidia.com, ryan_chen@aspeedtech.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 2/2] gpio: aspeed: Add support for reset tolerance Date: Wed, 1 Nov 2017 15:04:57 +1100 Message-Id: <20171101040457.1200-3-andrew@aj.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171101040457.1200-1-andrew@aj.id.au> References: <20171101040457.1200-1-andrew@aj.id.au> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Use the new pinconf parameter for state persistence to expose the associated capability of the Aspeed GPIO controller. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley --- drivers/gpio/gpio-aspeed.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 00dc1c020198..3125dcb9211d 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -60,6 +60,7 @@ struct aspeed_gpio_bank { uint16_t val_regs; uint16_t irq_regs; uint16_t debounce_regs; + uint16_t tolerance_regs; const char names[4][3]; }; @@ -70,48 +71,56 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { .val_regs = 0x0000, .irq_regs = 0x0008, .debounce_regs = 0x0040, + .tolerance_regs = 0x001c, .names = { "A", "B", "C", "D" }, }, { .val_regs = 0x0020, .irq_regs = 0x0028, .debounce_regs = 0x0048, + .tolerance_regs = 0x003c, .names = { "E", "F", "G", "H" }, }, { .val_regs = 0x0070, .irq_regs = 0x0098, .debounce_regs = 0x00b0, + .tolerance_regs = 0x00ac, .names = { "I", "J", "K", "L" }, }, { .val_regs = 0x0078, .irq_regs = 0x00e8, .debounce_regs = 0x0100, + .tolerance_regs = 0x00fc, .names = { "M", "N", "O", "P" }, }, { .val_regs = 0x0080, .irq_regs = 0x0118, .debounce_regs = 0x0130, + .tolerance_regs = 0x012c, .names = { "Q", "R", "S", "T" }, }, { .val_regs = 0x0088, .irq_regs = 0x0148, .debounce_regs = 0x0160, + .tolerance_regs = 0x015c, .names = { "U", "V", "W", "X" }, }, { .val_regs = 0x01E0, .irq_regs = 0x0178, .debounce_regs = 0x0190, + .tolerance_regs = 0x018c, .names = { "Y", "Z", "AA", "AB" }, }, { - .val_regs = 0x01E8, - .irq_regs = 0x01A8, + .val_regs = 0x01e8, + .irq_regs = 0x01a8, .debounce_regs = 0x01c0, + .tolerance_regs = 0x01bc, .names = { "AC", "", "", "" }, }, }; @@ -534,6 +543,30 @@ static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, return 0; } +static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, + unsigned int offset, bool enable) +{ + struct aspeed_gpio *gpio = gpiochip_get_data(chip); + const struct aspeed_gpio_bank *bank; + unsigned long flags; + u32 val; + + bank = to_bank(offset); + + spin_lock_irqsave(&gpio->lock, flags); + val = readl(gpio->base + bank->tolerance_regs); + + if (enable) + val |= GPIO_BIT(offset); + else + val &= ~GPIO_BIT(offset); + + writel(val, gpio->base + bank->tolerance_regs); + spin_unlock_irqrestore(&gpio->lock, flags); + + return 0; +} + static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) { if (!have_gpio(gpiochip_get_data(chip), offset)) @@ -771,6 +804,8 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, param == PIN_CONFIG_DRIVE_OPEN_SOURCE) /* Return -ENOTSUPP to trigger emulation, as per datasheet */ return -ENOTSUPP; + else if (param == PIN_CONFIG_PERSIST_STATE) + return aspeed_gpio_reset_tolerance(chip, offset, arg); return -ENOTSUPP; }