Patchwork [2/3] target-arm: Fix soft interrupt in GIC distributor

login
register
mail settings
Submitter Adam Lackorzynski
Date Feb. 15, 2011, 10:49 a.m.
Message ID <20110215104915.GC19666@os.inf.tu-dresden.de>
Download mbox | patch
Permalink /patch/83232/
State New
Headers show

Comments

Adam Lackorzynski - Feb. 15, 2011, 10:49 a.m.
Fix selection of target list filter mode.

Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
---
 hw/arm_gic.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
Peter Maydell - Feb. 16, 2011, 1:50 p.m.
On 15 February 2011 10:49, Adam Lackorzynski <adam@os.inf.tu-dresden.de> wrote:
> Fix selection of target list filter mode.
>
> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
> ---
>  hw/arm_gic.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index e6b1953..0e934ec 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -549,10 +549,10 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
>             mask = (value >> 16) & ALL_CPU_MASK;
>             break;
>         case 1:
> -            mask = 1 << cpu;
> +            mask = ALL_CPU_MASK ^ (1 << cpu);
>             break;
>         case 2:
> -            mask = ALL_CPU_MASK ^ (1 << cpu);
> +            mask = 1 << cpu;
>             break;
>         default:
>             DPRINTF("Bad Soft Int target filter\n");

This looks like a good fix based on the TRM; however I don't have an
A9-based image to hand to test with so I've asked a colleague to give
it a quick smoke test before I formally mark it as reviewed-by me
(probably some time next week).

thanks
-- PMM
Peter Maydell - Feb. 21, 2011, 8:25 p.m.
On 15 February 2011 10:49, Adam Lackorzynski <adam@os.inf.tu-dresden.de> wrote:
> Fix selection of target list filter mode.
>
> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

-- PMM

Patch

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index e6b1953..0e934ec 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -549,10 +549,10 @@  static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
             mask = (value >> 16) & ALL_CPU_MASK;
             break;
         case 1:
-            mask = 1 << cpu;
+            mask = ALL_CPU_MASK ^ (1 << cpu);
             break;
         case 2:
-            mask = ALL_CPU_MASK ^ (1 << cpu);
+            mask = 1 << cpu;
             break;
         default:
             DPRINTF("Bad Soft Int target filter\n");