From patchwork Tue Oct 31 04:22:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832227 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQysG5vSsz9sRg for ; Tue, 31 Oct 2017 15:23:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752683AbdJaEXp (ORCPT ); Tue, 31 Oct 2017 00:23:45 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15616 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751499AbdJaEXp (ORCPT ); Tue, 31 Oct 2017 00:23:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Oct 2017 21:23:05 -0700 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:23:24 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 21:23:24 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:23:09 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:23:09 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 4/4] PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2 Date: Tue, 31 Oct 2017 09:52:49 +0530 Message-ID: <1509423769-10522-5-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> References: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org sets CLKREQ asserted delay to a higher value to avoid unnecessary wake up from L1.2_ENTRY state for Tegra210 Signed-off-by: Vidya Sagar --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 08da67a82a2d..811209dedde2 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -204,6 +204,8 @@ #define RP_L1_PM_SUBSTATES_1_CTL 0xC04 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK 0x1FFF #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY 0x26 +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK (0x1FF << 13) +#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY (0x27 << 13) #define RP_L1_PM_SUBSTATES_2_CTL 0xC08 #define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK 0x1FFF @@ -354,6 +356,7 @@ struct tegra_pcie_soc { bool updateFC_threshold; bool has_aspm_l1; bool has_aspm_l1ss; + bool l1ss_rp_wake_fixup; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2307,6 +2310,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) (7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT); writel(value, port->base + RP_L1_PM_SUBSTATES_CTL); + if (soc->l1ss_rp_wake_fixup) { + /* Set CLKREQ asserted delay greater than Power_Off + * time (2us) to avoid RP wakeup in L1.2_ENTRY + */ + value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); + value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK; + value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY; + writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL); + } + /* Following is based on clk_m being 19.2 MHz */ value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL); value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK; @@ -2464,6 +2477,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .updateFC_threshold = false, .has_aspm_l1 = false, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2487,6 +2501,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .updateFC_threshold = false, .has_aspm_l1 = true, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2509,6 +2524,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .updateFC_threshold = false, .has_aspm_l1 = true, .has_aspm_l1ss = false, + .l1ss_rp_wake_fixup = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2539,6 +2555,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .updateFC_threshold = true, .has_aspm_l1 = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2562,6 +2579,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .updateFC_threshold = false, .has_aspm_l1 = true, .has_aspm_l1ss = true, + .l1ss_rp_wake_fixup = false, }; static const struct of_device_id tegra_pcie_of_match[] = {