From patchwork Tue Oct 31 04:22:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQysD2Tbpz9sRg for ; Tue, 31 Oct 2017 15:23:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbdJaEXn (ORCPT ); Tue, 31 Oct 2017 00:23:43 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5875 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751499AbdJaEXm (ORCPT ); Tue, 31 Oct 2017 00:23:42 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 21:23:03 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:23:42 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 21:23:42 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:02 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:23:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:23:01 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:23:01 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 2/4] PCI: tegra: Enable ASPM-L1 capability advertisement Date: Tue, 31 Oct 2017 09:52:47 +0530 Message-ID: <1509423769-10522-3-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> References: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enables advertisement of ASPM-L1 support in capability registers of applicable Tegra chips Signed-off-by: Vidya Sagar --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index adae03d671ab..e1526cc5d381 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -226,6 +226,9 @@ #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) +#define RP_VEND_XP1 0xf04 +#define RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT BIT(21) + #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH (0x9 << 12) @@ -327,6 +330,7 @@ struct tegra_pcie_soc { bool RAW_violation_fixup; bool program_deskew_time; bool updateFC_threshold; + bool has_aspm_l1; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2188,6 +2192,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port) value = readl(port->base + RP_VEND_CTL1); value |= RP_VEND_CTL1_ERPT; writel(value, port->base + RP_VEND_CTL1); + + if (port->pcie->soc->has_aspm_l1) { + /* Advertise ASPM-L1 state capability*/ + value = readl(port->base + RP_VEND_XP1); + value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT; + writel(value, port->base + RP_VEND_XP1); + } } static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) @@ -2391,6 +2402,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2412,6 +2424,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2432,6 +2445,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .RAW_violation_fixup = true, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2460,6 +2474,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .RAW_violation_fixup = false, .program_deskew_time = true, .updateFC_threshold = true, + .has_aspm_l1 = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2481,6 +2496,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .RAW_violation_fixup = false, .program_deskew_time = false, .updateFC_threshold = false, + .has_aspm_l1 = true, }; static const struct of_device_id tegra_pcie_of_match[] = {