From patchwork Mon Oct 30 13:57:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbhj0S8kz9t2c for ; Tue, 31 Oct 2017 01:00:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752322AbdJ3OAD (ORCPT ); Mon, 30 Oct 2017 10:00:03 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8386 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752019AbdJ3OAD (ORCPT ); Mon, 30 Oct 2017 10:00:03 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 30 Oct 2017 06:59:51 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 07:00:10 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 07:00:10 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:57:44 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:57:43 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:57:43 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:57:43 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 01/12] PCI: tegra: Start LTSSM after programming root port Date: Mon, 30 Oct 2017 19:27:12 +0530 Message-ID: <1509371843-22931-2-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch ensures that LTSSM is started (by deasserting pcie_xrst) only after all the required root port register programming is completed. Signed-off-by: Manikanta Maddireddy --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 96e8038c3019..b41c60c7414c 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -1024,9 +1024,6 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* take the PCIe interface module out of reset */ - reset_control_deassert(pcie->pcie_xrst); - /* finally enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); value |= AFI_CONFIGURATION_EN_FPCI; @@ -1065,7 +1062,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie) dev_err(dev, "failed to power off PHY(s): %d\n", err); } - reset_control_assert(pcie->pcie_xrst); reset_control_assert(pcie->afi_rst); reset_control_assert(pcie->pex_rst); @@ -2116,7 +2112,12 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) port->index, port->lanes); tegra_pcie_port_enable(port); + } + /* take the PCIe interface module out of reset */ + reset_control_deassert(pcie->pcie_xrst); + + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { if (tegra_pcie_port_check_link(port)) continue;