From patchwork Mon Oct 30 13:57:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 832044 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQbgY3Nkyz9t1G for ; Tue, 31 Oct 2017 00:59:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752274AbdJ3N7E (ORCPT ); Mon, 30 Oct 2017 09:59:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17825 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752212AbdJ3N7E (ORCPT ); Mon, 30 Oct 2017 09:59:04 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 30 Oct 2017 06:58:35 -0700 Received: from HQMAIL108.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 06:59:11 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 30 Oct 2017 06:59:11 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:26 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 13:58:25 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 13:58:25 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 06:58:25 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V3 07/12] PCI: tegra: Disable AFI dynamic clock gating Date: Mon, 30 Oct 2017 19:27:18 +0530 Message-ID: <1509371843-22931-8-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> References: <1509371843-22931-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org When there are 32 outstanding writes from AFI to memory, the outstanding write counter overflows and indicates that there are "0" outstanding write transactions. This outstanding write counter is used to generate IDLE signal to dynamically gate the AFI clock. When memory controller is under heavy load, its possible that write completions will come back to AFI after long delay and AFI write counter overflows. AFI clock gets gated even when there are outstanding transactions towards memory controller resutling in system hang. Disable dynamic clock gating of AFI clock to avoid system hang. Signed-off-by: Manikanta Maddireddy --- V3: * no change in this patch V2: * no change in this patch drivers/pci/host/pci-tegra.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 4562b0c113a8..c264037112cb 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -103,8 +103,9 @@ #define AFI_MSI_EN_VEC6 0xa4 #define AFI_MSI_EN_VEC7 0xa8 -#define AFI_CONFIGURATION 0xac -#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION 0xac +#define AFI_CONFIGURATION_EN_FPCI (1 << 0) +#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31) #define AFI_FPCI_ERROR_MASKS 0xb0 @@ -1059,9 +1060,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) } } - /* finally enable PCIe */ + /* Disable AFI dynamic clock gating and enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); - value |= AFI_CONFIGURATION_EN_FPCI; + value |= (AFI_CONFIGURATION_EN_FPCI | + AFI_CONFIGURATION_CLKEN_OVERRIDE); afi_writel(pcie, value, AFI_CONFIGURATION); value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |