From patchwork Tue Feb 15 04:56:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qemu@gibson.dropbear.id.au X-Patchwork-Id: 83198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2CF1FB7117 for ; Tue, 15 Feb 2011 17:56:27 +1100 (EST) Received: from localhost ([127.0.0.1]:36533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PpDFj-0007rt-0B for incoming@patchwork.ozlabs.org; Tue, 15 Feb 2011 00:15:07 -0500 Received: from [140.186.70.92] (port=53431 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PpCyI-0008U8-D0 for qemu-devel@nongnu.org; Mon, 14 Feb 2011 23:57:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PpCyH-0001gA-2l for qemu-devel@nongnu.org; Mon, 14 Feb 2011 23:57:06 -0500 Received: from ozlabs.org ([203.10.76.45]:34737) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PpCyG-0001aL-DV for qemu-devel@nongnu.org; Mon, 14 Feb 2011 23:57:04 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 88CEAB7128; Tue, 15 Feb 2011 15:56:53 +1100 (EST) From: qemu@gibson.dropbear.id.au To: qemu-devel@nongnu.org Date: Tue, 15 Feb 2011 15:56:22 +1100 Message-Id: <1297745799-26148-12-git-send-email-qemu@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1297745799-26148-1-git-send-email-qemu@gibson.dropbear.id.au> References: <1297745799-26148-1-git-send-email-qemu@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 203.10.76.45 Cc: paulus@samba.org, agraf@suse.de, anton@samba.org Subject: [Qemu-devel] [PATCH 11/28] Better factor the ppc hash translation path X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: David Gibson Currently the path handling hash page table translation in get_segment() has a mix of common and 32 or 64 bit specific code. However the division is not done terribly well which results in a lot of messy code flipping between common and divided paths. This patch improves the organization, consolidating several divided paths into one. This in turn allows simplification of some code in get_segment(), removing a number of ugly interim variables. This new factorization will also make it easier to add support for the 1T segments added in newer CPUs. Signed-off-by: David Gibson --- target-ppc/cpu.h | 1 + target-ppc/helper.c | 68 +++++++++++++++------------------------------------ 2 files changed, 21 insertions(+), 48 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 592907a..71f8d72 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -386,6 +386,7 @@ struct ppc_slb_t { #define SLB_VSID_B 0xc000000000000000ULL #define SLB_VSID_B_256M 0x0000000000000000ULL #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL +#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID) #define SLB_VSID_KS 0x0000000000000800ULL #define SLB_VSID_KP 0x0000000000000400ULL #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */ diff --git a/target-ppc/helper.c b/target-ppc/helper.c index b9438b2..111675d 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -657,29 +657,15 @@ static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h, return ret; } -static inline int find_pte32(CPUState *env, mmu_ctx_t *ctx, int h, int rw, - int type, int target_page_bits) -{ - return _find_pte(env, ctx, 0, h, rw, type, target_page_bits); -} - -#if defined(TARGET_PPC64) -static inline int find_pte64(CPUState *env, mmu_ctx_t *ctx, int h, int rw, - int type, int target_page_bits) -{ - return _find_pte(env, ctx, 1, h, rw, type, target_page_bits); -} -#endif - static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw, int type, int target_page_bits) { #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) - return find_pte64(env, ctx, h, rw, type, target_page_bits); + return _find_pte(env, ctx, 1, h, rw, type, target_page_bits); #endif - return find_pte32(env, ctx, h, rw, type, target_page_bits); + return _find_pte(env, ctx, 0, h, rw, type, target_page_bits); } #if defined(TARGET_PPC64) @@ -799,14 +785,16 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int type) { target_phys_addr_t hash; - target_ulong sr, vsid, pgidx, page_mask; + target_ulong vsid; int ds, pr, target_page_bits; int ret, ret2; pr = msr_pr; + ctx->eaddr = eaddr; #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { ppc_slb_t *slb; + target_ulong pageaddr; LOG_MMU("Check SLBs\n"); slb = slb_lookup(env, eaddr); @@ -815,19 +803,24 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, } vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; - page_mask = ~SEGMENT_MASK_256M; target_page_bits = (slb->vsid & SLB_VSID_L) ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS; ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP) : (slb->vsid & SLB_VSID_KS)); ds = 0; ctx->nx = !!(slb->vsid & SLB_VSID_N); - ctx->eaddr = eaddr; + + pageaddr = eaddr & ((1ULL << 28) - (1ULL << target_page_bits)); + /* XXX: this is false for 1 TB segments */ + hash = vsid ^ (pageaddr >> target_page_bits); + /* Only 5 bits of the page index are used in the AVPN */ + ctx->ptem = (slb->vsid & SLB_VSID_PTEM) | ((pageaddr >> 16) & 0x0F80); } else #endif /* defined(TARGET_PPC64) */ { + target_ulong sr, pgidx; + sr = env->sr[eaddr >> 28]; - page_mask = 0x0FFFFFFF; ctx->key = (((sr & 0x20000000) && (pr != 0)) || ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; ds = sr & 0x80000000 ? 1 : 0; @@ -839,6 +832,9 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, " ir=%d dr=%d pr=%d %d t=%d\n", eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0, rw, type); + pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits; + hash = vsid ^ pgidx; + ctx->ptem = (vsid << 7) | (pgidx >> 10); } LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid); @@ -847,36 +843,12 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, /* Check if instruction fetch is allowed, if needed */ if (type != ACCESS_CODE || ctx->nx == 0) { /* Page address translation */ - pgidx = (eaddr & page_mask) >> target_page_bits; -#if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { - /* XXX: this is false for 1 TB segments */ - hash = vsid ^ pgidx; - } else -#endif - { - hash = vsid ^ pgidx; - } LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx " hash " TARGET_FMT_plx "\n", env->htab_base, env->htab_mask, hash); ctx->hash[0] = hash; ctx->hash[1] = ~hash; -#if defined(TARGET_PPC64) - if (env->mmu_model & POWERPC_MMU_64) { - /* Only 5 bits of the page index are used in the AVPN */ - if (target_page_bits > 23) { - ctx->ptem = (vsid << 12) | - ((pgidx << (target_page_bits - 16)) & 0xF80); - } else { - ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); - } - } else -#endif - { - ctx->ptem = (vsid << 7) | (pgidx >> 10); - } /* Initialize real address with an invalid value */ ctx->raddr = (target_phys_addr_t)-1ULL; if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || @@ -885,9 +857,9 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); } else { LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx - " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx + " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx " hash=" TARGET_FMT_plx "\n", - env->htab_base, env->htab_mask, vsid, pgidx, + env->htab_base, env->htab_mask, vsid, ctx->ptem, ctx->hash[0]); /* Primary table lookup */ ret = find_pte(env, ctx, 0, rw, type, target_page_bits); @@ -895,9 +867,9 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx, /* Secondary table lookup */ if (eaddr != 0xEFFFFFFF) LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx - " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx + " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx " hash=" TARGET_FMT_plx "\n", - env->htab_base, env->htab_mask, vsid, pgidx, + env->htab_base, env->htab_mask, vsid, ctx->ptem, ctx->hash[1]); ret2 = find_pte(env, ctx, 1, rw, type, target_page_bits);