From patchwork Thu Oct 26 15:28:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Edlinger X-Patchwork-Id: 830769 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yN9s94NbDz9s03 for ; Fri, 27 Oct 2017 02:29:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932506AbdJZP2S convert rfc822-to-8bit (ORCPT ); Thu, 26 Oct 2017 11:28:18 -0400 Received: from mail-oln040092070075.outbound.protection.outlook.com ([40.92.70.75]:58269 "EHLO EUR03-AM5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932499AbdJZP2P (ORCPT ); Thu, 26 Oct 2017 11:28:15 -0400 Received: from AM5EUR03FT025.eop-EUR03.prod.protection.outlook.com (10.152.16.58) by AM5EUR03HT129.eop-EUR03.prod.protection.outlook.com (10.152.17.178) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.20.156.4; Thu, 26 Oct 2017 15:28:13 +0000 Received: from AM5PR0701MB2657.eurprd07.prod.outlook.com (10.152.16.60) by AM5EUR03FT025.mail.protection.outlook.com (10.152.16.157) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.20.156.4 via Frontend Transport; Thu, 26 Oct 2017 15:28:13 +0000 Received: from AM5PR0701MB2657.eurprd07.prod.outlook.com ([fe80::6432:5809:c70:3d63]) by AM5PR0701MB2657.eurprd07.prod.outlook.com ([fe80::6432:5809:c70:3d63%17]) with mapi id 15.20.0197.004; Thu, 26 Oct 2017 15:28:13 +0000 From: Bernd Edlinger To: Linus Walleij CC: Rob Herring , Christian Lamparter , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: [PATCHv5 1/2] Add device tree bindings for Altera FPGA Manager GPIO Thread-Topic: [PATCHv5 1/2] Add device tree bindings for Altera FPGA Manager GPIO Thread-Index: AQHTTm5meollfqP9S0eoO25uH9S8hA== Date: Thu, 26 Oct 2017 15:28:13 +0000 Message-ID: Accept-Language: de-DE, en-US Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: kernel.org; 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RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM5EUR03HT129; x-forefront-prvs: 04724A515E x-forefront-antispam-report: SFV:NSPM; SFS:(7070007)(98901004); DIR:OUT; SFP:1901; SCL:1; SRVR:AM5EUR03HT129; H:AM5PR0701MB2657.eurprd07.prod.outlook.com; FPR:; SPF:None; LANG:; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5283619f-7bdc-4f2f-c0a1-08d51c862c59 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Oct 2017 15:28:13.7599 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5EUR03HT129 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Signed-off-by: Bernd Edlinger --- .../bindings/gpio/gpio-altera-fpgamgr.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-altera-fpgamgr.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-altera-fpgamgr.txt b/Documentation/devicetree/bindings/gpio/gpio-altera-fpgamgr.txt new file mode 100644 index 0000000..6e2ad47 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-altera-fpgamgr.txt @@ -0,0 +1,43 @@ +Altera FPGA Manager GPIO controller bindings + +Required controller properties: +- #address-cells : Should be 1 +- #size-cells : Should be 0 +- compatible: + - "altr,fpgamgr-gpio" +- reg: Physical base address and length of the controller's registers. + +The FPGA Manager has two 32-bit ports, one for input and one for output. + +Port properties: +- compatible: + - "altr,fpgamgr-gpio-output" + - "altr,fpgamgr-gpio-input" +- #gpio-cells : Should be 2 + - The first cell is the gpio offset number. + - The second cell is reserved and is currently unused. +- gpio-controller : Marks the device node as a GPIO controller. +- reg : Port number, 0 for output, 1 for input. + +Example: + +gpio3: gpio@ff706010 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,fpgamgr-gpio"; + reg = <0xff706010 0x8>; + + portd: gpio-controller@0 { + compatible = "altr,fpgamgr-gpio-output"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + }; + + porte: gpio-controller@1 { + compatible = "altr,fpgamgr-gpio-input"; + gpio-controller; + #gpio-cells = <2>; + reg = <1>; + }; +};