From patchwork Mon Oct 23 13:08:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe Bergheaud X-Patchwork-Id: 829293 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yLGvg6Dh5z9t6C for ; Tue, 24 Oct 2017 00:09:35 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yLGvg4TBwzDqjm for ; Tue, 24 Oct 2017 00:09:35 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=felix@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yLGvY3wb4zDqhg for ; Tue, 24 Oct 2017 00:09:29 +1100 (AEDT) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v9ND4opd018747 for ; Mon, 23 Oct 2017 09:09:26 -0400 Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) by mx0b-001b2d01.pphosted.com with ESMTP id 2dsd4kk0h6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 23 Oct 2017 09:09:26 -0400 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 23 Oct 2017 14:09:22 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v9ND9LaK23789774; Mon, 23 Oct 2017 13:09:21 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6DE2A52045; Mon, 23 Oct 2017 13:03:34 +0100 (BST) Received: from smtp.lab.toulouse-stg.fr.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 5B14E52043; Mon, 23 Oct 2017 13:03:34 +0100 (BST) Received: from w541.lab.toulouse-stg.fr.ibm.com (t42p.lab.toulouse-stg.fr.ibm.com [9.101.4.37]) by smtp.lab.toulouse-stg.fr.ibm.com (Postfix) with ESMTP id 49ADC220076; Mon, 23 Oct 2017 15:09:21 +0200 (CEST) From: Philippe Bergheaud To: skiboot@lists.ozlabs.org Date: Mon, 23 Oct 2017 15:08:30 +0200 X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171023130830.18818-1-felix@linux.vnet.ibm.com> References: <20171023130830.18818-1-felix@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17102313-0040-0000-0000-00000405EFC1 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17102313-0041-0000-0000-000020A85809 Message-Id: <20171023130830.18818-2-felix@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-10-23_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1710230187 Subject: [Skiboot] [PATCH 2/2] phb4: set PBCQ Tunnel BAR for tunneled operations X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" P9 supports PCI tunneled operations (atomics and as_notify) that require setting the PBCQ Tunnel BAR Response register with an address mask. This register is currently initialized by enable_capi_mode(). As tunneled operations may also operate in PCI mode, a new API is required to set the PBCQ Tunnel BAR Response register without switching to CAPI mode. This patch provides two new OPAL calls to get/set the PBCQ Tunnel BAR Response register. This new API aims at letting devices drivers set the PBCQ Tunnel BAR. Compatibility with older kernel versions is made by enable_capi_mode(). Signed-off-by: Philippe Bergheaud Reviewed-by: Christophe Lombard --- core/pci-opal.c | 33 +++++++++++++++++++++++++++ hw/phb4.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++----- include/opal-api.h | 4 +++- include/pci.h | 4 ++++ 4 files changed, 100 insertions(+), 6 deletions(-) diff --git a/core/pci-opal.c b/core/pci-opal.c index bbbbcd5d..d7f4230a 100644 --- a/core/pci-opal.c +++ b/core/pci-opal.c @@ -1052,3 +1052,36 @@ static int64_t opal_pci_set_phb_cmpm(uint64_t phb_id, uint64_t phb_reg, return rc; } opal_call(OPAL_PCI_SET_PHB_CMPM, opal_pci_set_phb_cmpm, 3); + +static int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb) + return OPAL_PARAMETER; + if (!phb->ops->get_tunnel_bar) + return OPAL_UNSUPPORTED; + + phb_lock(phb); + phb->ops->get_tunnel_bar(phb, addr); + phb_unlock(phb); + return OPAL_SUCCESS; +} +opal_call(OPAL_PCI_GET_PBCQ_TUNNEL_BAR, opal_pci_get_pbcq_tunnel_bar, 2); + +static int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr) +{ + struct phb *phb = pci_get_phb(phb_id); + int64_t rc; + + if (!phb) + return OPAL_PARAMETER; + if (!phb->ops->set_tunnel_bar) + return OPAL_UNSUPPORTED; + + phb_lock(phb); + rc = phb->ops->set_tunnel_bar(phb, addr); + phb_unlock(phb); + return rc; +} +opal_call(OPAL_PCI_SET_PBCQ_TUNNEL_BAR, opal_pci_set_pbcq_tunnel_bar, 2); diff --git a/hw/phb4.c b/hw/phb4.c index 1add8a75..54dd9fac 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3751,12 +3751,18 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, out_be64(p->regs + PHB_ASN_CMPM, reg); } - /* PBCQ Tunnel Bar Register - * Write Tunnel register to match PSL TNR register + /* + * PBCQ Tunnel Bar Register + * If unset, then use PSL_TNR_ADDR[TNR_Addr] reset value. */ - xscom_write(p->chip_id, - p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, - 0x020000E000000000); + xscom_read(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, ®); + if (!reg) { + reg = 0x020000e000000000ull; + xscom_write(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, + reg); + } /* PB AIB Hardware Control Register * Wait 32 PCI clocks for a credit to become available @@ -4092,6 +4098,53 @@ static int64_t phb4_set_cmpm(struct phb *phb, uint64_t phb_reg, uint64_t ind) return OPAL_SUCCESS; } +/* + * Return the address out of a PBCQ Tunnel Bar register. + */ +static void phb4_get_tunnel_bar(struct phb *phb, uint64_t *addr) +{ + struct phb4 *p = phb_to_phb4(phb); + uint64_t val; + + xscom_read(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, + &val); + *addr = val >> 8; +} + +/* + * Set PBCQ Tunnel Bar register. + * Store addr bits [8:50] in PBCQ Tunnel Bar register bits [0:42]. + * Note that addr bits [8:50] must also match PSL_TNR_ADDR[8:50]. + * Reset register if val == 0. + * + * This interface is required to let device drivers set the Tunnel Bar + * value of their choice. + * + * Compatibility with older versions of linux, that do not set the + * Tunnel Bar with phb4_set_tunnel_bar(), is ensured by enable_capi_mode(), + * that will set the default value that used to be assumed. + */ +static int64_t phb4_set_tunnel_bar(struct phb *phb, uint64_t addr) +{ + struct phb4 *p = phb_to_phb4(phb); + uint64_t mask = 0x00ffffffffffe000ull; + + if (! addr) { + /* Reset register */ + xscom_write(p->chip_id, + p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, addr); + return OPAL_SUCCESS; + } + if ((addr & ~mask)) + return OPAL_PARAMETER; + if (!(addr & mask)) + return OPAL_PARAMETER; + + xscom_write(p->chip_id, p->pe_stk_xscom + XPEC_NEST_STK_TUNNEL_BAR, + (addr & mask) << 8); + return OPAL_SUCCESS; +} + static const struct phb_ops phb4_ops = { .cfg_read8 = phb4_pcicfg_read8, .cfg_read16 = phb4_pcicfg_read16, @@ -4129,6 +4182,8 @@ static const struct phb_ops phb4_ops = { .set_capp_recovery = phb4_set_capp_recovery, .get_cmpm = phb4_get_cmpm, .set_cmpm = phb4_set_cmpm, + .get_tunnel_bar = phb4_get_tunnel_bar, + .set_tunnel_bar = phb4_set_tunnel_bar, }; static void phb4_init_ioda3(struct phb4 *p) diff --git a/include/opal-api.h b/include/opal-api.h index ce948136..1e9715ee 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -216,7 +216,9 @@ #define OPAL_PCI_SET_P2P 157 #define OPAL_PCI_GET_PHB_CMPM 158 #define OPAL_PCI_SET_PHB_CMPM 159 -#define OPAL_LAST 159 +#define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 160 +#define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 161 +#define OPAL_LAST 161 /* Device tree flags */ diff --git a/include/pci.h b/include/pci.h index cdf82ee8..5276b574 100644 --- a/include/pci.h +++ b/include/pci.h @@ -337,6 +337,10 @@ struct phb_ops { /* Get/set PHB Compare/Mask registers */ int64_t (*get_cmpm)(struct phb *phb, uint64_t phb_reg, uint64_t *ind); int64_t (*set_cmpm)(struct phb *phb, uint64_t phb_reg, uint64_t ind); + + /* Get/set PBCQ Tunnel BAR register */ + void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr); + int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr); }; enum phb_type {