From patchwork Sat Feb 12 00:15:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 82879 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C24DFB70A7 for ; Sat, 12 Feb 2011 11:17:09 +1100 (EST) Received: from localhost ([127.0.0.1]:50191 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Po3Aa-0002rG-Rz for incoming@patchwork.ozlabs.org; Fri, 11 Feb 2011 19:17:00 -0500 Received: from [140.186.70.92] (port=50634 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Po39Q-0002r2-NN for qemu-devel@nongnu.org; Fri, 11 Feb 2011 19:15:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Po39P-0003rw-OE for qemu-devel@nongnu.org; Fri, 11 Feb 2011 19:15:48 -0500 Received: from mail-ey0-f173.google.com ([209.85.215.173]:61114) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Po39P-0003rs-Gu for qemu-devel@nongnu.org; Fri, 11 Feb 2011 19:15:47 -0500 Received: by eyg7 with SMTP id 7so1642429eyg.4 for ; Fri, 11 Feb 2011 16:15:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:subject:date:message-id:x-mailer; bh=qTuJ0GBvUb1KLEoEoH9lK5zPswC9xIFqoXUR6AW9MwM=; b=Fo4hxBPjs8ifGoes4ILKxWlIRpIOUKr5mi969YsUAOgadBp6zP4l87GU1SxxtKu8a3 5VYLhW2nAhjz8ezOq3enx2r71ZO8QXPnwxMmNtRVUvwzPhmGTE5gwWuy/4AWrweT8Acf fCUPUFLZ2VPchERkNdb8L9vZX7c2ANX89BWOU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:message-id:x-mailer; b=aL2XYdYp1GSUZ2RUKN1QVCVqmK+F8BnrQEyCAUph4PRQQ33AqBrSHB2pVQPCVO8N3D abWfla8aaXBT88pFqCQlzXu5AD4z51WHOMHnX5iiZpo1JicGb5y9HfHjm7QAPDRwInQd kEKQ0adTQ2sk8g1MVH81Kgp95eQu3YQfpnPMw= Received: by 10.14.45.74 with SMTP id o50mr1137636eeb.28.1297469746608; Fri, 11 Feb 2011 16:15:46 -0800 (PST) Received: from doriath.ww600.siemens.net (ppp89-110-8-230.pppoe.avangarddsl.ru [89.110.8.230]) by mx.google.com with ESMTPS id t5sm1202197eeh.20.2011.02.11.16.15.43 (version=SSLv3 cipher=OTHER); Fri, 11 Feb 2011 16:15:45 -0800 (PST) From: Dmitry Eremin-Solenikov To: qemu-devel@nongnu.org Date: Sat, 12 Feb 2011 03:15:23 +0300 Message-Id: <1297469725-31730-1-git-send-email-dbaryshkov@gmail.com> X-Mailer: git-send-email 1.7.2.3 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.215.173 Subject: [Qemu-devel] [PATCH 1/3] mainstone: correct and simplify irq handling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Simplify IRQ handling to stop setting an input irq pin. As a win, also get correct IRQ status after save/load cycle. Signed-off-by: Dmitry Eremin-Solenikov --- hw/mst_fpga.c | 29 ++++++++++------------------- 1 files changed, 10 insertions(+), 19 deletions(-) diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index 93c6514..3c594b8 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -46,33 +46,21 @@ typedef struct mst_irq_state{ }mst_irq_state; static void -mst_fpga_update_gpio(mst_irq_state *s) -{ - uint32_t level, diff; - int bit; - level = s->prev_level ^ s->intsetclr; - - for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { - bit = ffs(diff) - 1; - qemu_set_irq(s->pins[bit], (level >> bit) & 1 ); - } - s->prev_level = level; -} - -static void mst_fpga_set_irq(void *opaque, int irq, int level) { mst_irq_state *s = (mst_irq_state *)opaque; + uint32_t oldint = s->intsetclr; if (level) s->prev_level |= 1u << irq; else s->prev_level &= ~(1u << irq); - if(s->intmskena & (1u << irq)) { - s->intsetclr = 1u << irq; - qemu_set_irq(s->parent, level); - } + if ((s->intmskena & (1u << irq)) && level) + s->intsetclr |= 1u << irq; + + if (oldint != (s->intsetclr & s->intmskena)) + qemu_set_irq(s->parent, s->intsetclr & s->intmskena); } @@ -146,10 +134,11 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) break; case MST_INTMSKENA: /* Mask interupt */ s->intmskena = (value & 0xFEEFF); - mst_fpga_update_gpio(s); + qemu_set_irq(s->parent, s->intsetclr & s->intmskena); break; case MST_INTSETCLR: /* clear or set interrupt */ s->intsetclr = (value & 0xFEEFF); + qemu_set_irq(s->parent, s->intsetclr); break; case MST_PCMCIA0: s->pcmcia0 = value; @@ -212,6 +201,8 @@ mst_fpga_load(QEMUFile *f, void *opaque, int version_id) qemu_get_be32s(f, &s->intsetclr); qemu_get_be32s(f, &s->pcmcia0); qemu_get_be32s(f, &s->pcmcia1); + + qemu_set_irq(s->parent, s->intsetclr & s->intmskena); return 0; }