[v2] dmaengine: tegra-apb: Support non-flow controlled slave configuration

Message ID 20171019221308.18707-1-digetx@gmail.com
State New
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  • [v2] dmaengine: tegra-apb: Support non-flow controlled slave configuration
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Commit Message

Dmitry Osipenko Oct. 19, 2017, 10:13 p.m.
This allows DMA client to issue a non-flow controlled TX. In particular
it is needed for the fuse driver that reads fuse registers using APBDMA
to workaround a HW bug that results in hang when CPU and DMA perform
simultaneous access to fuse peripheral.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---

Change log:

v2:
	- Removed trailing whitespace reported by checkpatch

 drivers/dma/tegra20-apb-dma.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

Comments

Dmitry Osipenko Nov. 14, 2017, 11:23 a.m. | #1
On 20.10.2017 01:13, Dmitry Osipenko wrote:
> This allows DMA client to issue a non-flow controlled TX. In particular
> it is needed for the fuse driver that reads fuse registers using APBDMA
> to workaround a HW bug that results in hang when CPU and DMA perform
> simultaneous access to fuse peripheral.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

Vinod, are you going to apply this patch for 4.15?
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Vinod Koul Nov. 15, 2017, 3:54 p.m. | #2
On Tue, Nov 14, 2017 at 02:23:07PM +0300, Dmitry Osipenko wrote:
> On 20.10.2017 01:13, Dmitry Osipenko wrote:
> > This allows DMA client to issue a non-flow controlled TX. In particular
> > it is needed for the fuse driver that reads fuse registers using APBDMA
> > to workaround a HW bug that results in hang when CPU and DMA perform
> > simultaneous access to fuse peripheral.
> > 
> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> 
> Vinod, are you going to apply this patch for 4.15?

Sorry I dont seem to have this one in my queue and dont see it applied, not
sure why. Can you guys resend please
Dmitry Osipenko Nov. 16, 2017, 5:16 p.m. | #3
On 15.11.2017 18:54, Vinod Koul wrote:
> On Tue, Nov 14, 2017 at 02:23:07PM +0300, Dmitry Osipenko wrote:
>> On 20.10.2017 01:13, Dmitry Osipenko wrote:
>>> This allows DMA client to issue a non-flow controlled TX. In particular
>>> it is needed for the fuse driver that reads fuse registers using APBDMA
>>> to workaround a HW bug that results in hang when CPU and DMA perform
>>> simultaneous access to fuse peripheral.
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>>
>> Vinod, are you going to apply this patch for 4.15?
> 
> Sorry I dont seem to have this one in my queue and dont see it applied, not
> sure why. Can you guys resend please
> 

No problem, re-sent.
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Patch

diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index b9d75a54c896..9a558e30c461 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -353,7 +353,8 @@  static int tegra_dma_slave_config(struct dma_chan *dc,
 	}
 
 	memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
-	if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) {
+	if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
+	    sconfig->device_fc) {
 		if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
 			return -EINVAL;
 		tdc->slave_id = sconfig->slave_id;
@@ -970,8 +971,13 @@  static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 					TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 	ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 
-	csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
-	csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	csr |= TEGRA_APBDMA_CSR_ONCE;
+
+	if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
+		csr |= TEGRA_APBDMA_CSR_FLOW;
+		csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	}
+
 	if (flags & DMA_PREP_INTERRUPT)
 		csr |= TEGRA_APBDMA_CSR_IE_EOC;
 
@@ -1110,10 +1116,13 @@  static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
 					TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 	ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 
-	csr |= TEGRA_APBDMA_CSR_FLOW;
+	if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
+		csr |= TEGRA_APBDMA_CSR_FLOW;
+		csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
+	}
+
 	if (flags & DMA_PREP_INTERRUPT)
 		csr |= TEGRA_APBDMA_CSR_IE_EOC;
-	csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 
 	apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;