From patchwork Fri Feb 11 20:57:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 82831 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B8E2FB718F for ; Sat, 12 Feb 2011 08:01:18 +1100 (EST) Received: from localhost ([127.0.0.1]:49982 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Po079-0000B2-6v for incoming@patchwork.ozlabs.org; Fri, 11 Feb 2011 16:01:15 -0500 Received: from [140.186.70.92] (port=42251 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Po05b-00009Z-4M for qemu-devel@nongnu.org; Fri, 11 Feb 2011 15:59:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Po05Z-0003P7-St for qemu-devel@nongnu.org; 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Fri, 11 Feb 2011 12:58:00 -0800 (PST) Received: from doriath.ww600.siemens.net (ppp89-110-8-230.pppoe.avangarddsl.ru [89.110.8.230]) by mx.google.com with ESMTPS id c11sm618019fav.2.2011.02.11.12.57.59 (version=SSLv3 cipher=OTHER); Fri, 11 Feb 2011 12:58:00 -0800 (PST) From: Dmitry Eremin-Solenikov To: qemu-devel@nongnu.org Date: Fri, 11 Feb 2011 23:57:35 +0300 Message-Id: <1297457859-15685-3-git-send-email-dbaryshkov@gmail.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297457859-15685-1-git-send-email-dbaryshkov@gmail.com> References: <1297457859-15685-1-git-send-email-dbaryshkov@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.45 Subject: [Qemu-devel] [PATCH 3/7] mainstone: pass one irq to the mst_fpga instead of the whole PIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Dmitry Eremin-Solenikov --- hw/mainstone.c | 2 +- hw/mainstone.h | 2 +- hw/mst_fpga.c | 12 ++++++------ 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/mainstone.c b/hw/mainstone.c index 58e3f86..18d1415 100644 --- a/hw/mainstone.c +++ b/hw/mainstone.c @@ -117,7 +117,7 @@ static void mainstone_common_init(ram_addr_t ram_size, } } - mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0); + mst_irq = mst_irq_init(MST_FPGA_PHYS, cpu->pic[PXA2XX_PIC_GPIO_0]); /* setup keypad */ printf("map addr %p\n", &map); diff --git a/hw/mainstone.h b/hw/mainstone.h index 9618c06..35329f1 100644 --- a/hw/mainstone.h +++ b/hw/mainstone.h @@ -33,6 +33,6 @@ #define S1_IRQ 15 extern qemu_irq -*mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq); +*mst_irq_init(uint32_t base, qemu_irq irq); #endif /* __MAINSTONE_H__ */ diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c index 5252fc5..b59352b 100644 --- a/hw/mst_fpga.c +++ b/hw/mst_fpga.c @@ -28,7 +28,7 @@ #define MST_PCMCIA1 0xe4 typedef struct mst_irq_state{ - qemu_irq *parent; + qemu_irq parent; qemu_irq *pins; uint32_t prev_level; @@ -72,7 +72,7 @@ mst_fpga_set_irq(void *opaque, int irq, int level) if(s->intmskena & (1u << irq)) { s->intsetclr = 1u << irq; - qemu_set_irq(s->parent[0], level); + qemu_set_irq(s->parent, level); } } @@ -109,7 +109,7 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr) return s->pcmcia1; default: printf("Mainstone - mst_fpga_readb: Bad register offset " - REG_FMT " \n", addr); + "0x" TARGET_FMT_plx " \n", addr); } return 0; } @@ -160,7 +160,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) break; default: printf("Mainstone - mst_fpga_writeb: Bad register offset " - REG_FMT " \n", addr); + "0x" TARGET_FMT_plx " \n", addr); } } @@ -216,7 +216,7 @@ mst_fpga_load(QEMUFile *f, void *opaque, int version_id) return 0; } -qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq) +qemu_irq *mst_irq_init(uint32_t base, qemu_irq irq) { mst_irq_state *s; int iomemtype; @@ -225,7 +225,7 @@ qemu_irq *mst_irq_init(PXA2xxState *cpu, uint32_t base, int irq) s = (mst_irq_state *) qemu_mallocz(sizeof(mst_irq_state)); - s->parent = &cpu->pic[irq]; + s->parent = irq; /* alloc the external 16 irqs */ qi = qemu_allocate_irqs(mst_fpga_set_irq, s, MST_NUM_IRQS);