From patchwork Thu Feb 10 23:12:06 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 82686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 60697B7126 for ; Fri, 11 Feb 2011 10:16:26 +1100 (EST) Received: from localhost ([127.0.0.1]:41033 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PnfkM-0004KD-MO for incoming@patchwork.ozlabs.org; Thu, 10 Feb 2011 18:16:22 -0500 Received: from [140.186.70.92] (port=41304 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pnfgt-0002oE-GY for qemu-devel@nongnu.org; Thu, 10 Feb 2011 18:12:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pnfgo-0003g3-U1 for qemu-devel@nongnu.org; Thu, 10 Feb 2011 18:12:47 -0500 Received: from mail.serverraum.org ([78.47.150.89]:45101) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pnfgo-0003fS-6a for qemu-devel@nongnu.org; Thu, 10 Feb 2011 18:12:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.serverraum.org (Postfix) with ESMTP id 9EDBB3EEFE; Fri, 11 Feb 2011 00:12:41 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at mail.serverraum.org Received: from mail.serverraum.org ([127.0.0.1]) by localhost (web.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id igtEr6bcq32U; Fri, 11 Feb 2011 00:12:41 +0100 (CET) Received: from thanatos.fritz.box (91-66-128-56-dynip.superkabel.de [91.66.128.56]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.serverraum.org (Postfix) with ESMTPSA id 17C273EF07; Fri, 11 Feb 2011 00:12:41 +0100 (CET) From: Michael Walle To: qemu-devel@nongnu.org Date: Fri, 11 Feb 2011 00:12:06 +0100 Message-Id: <1297379530-23487-14-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1297379530-23487-1-git-send-email-michael@walle.cc> References: <1297379530-23487-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 78.47.150.89 Cc: "Edgar E. Iglesias" , Michael Walle , Alexander Graf , Richard Henderson Subject: [Qemu-devel] [PATCH 13/17] lm32: EVR32 and uclinux BSP X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds support for the following two BSPs: - LM32 EVR32 BSP (as used by RTEMS) - uclinux BSP by Theobroma Systems Signed-off-by: Michael Walle --- Makefile.target | 3 + default-configs/lm32-softmmu.mak | 4 + hw/lm32_boards.c | 295 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 302 insertions(+), 0 deletions(-) create mode 100644 default-configs/lm32-softmmu.mak create mode 100644 hw/lm32_boards.c diff --git a/Makefile.target b/Makefile.target index 185cc96..77d1ea3 100644 --- a/Makefile.target +++ b/Makefile.target @@ -247,6 +247,9 @@ obj-ppc-y += xilinx_timer.o obj-ppc-y += xilinx_uartlite.o obj-ppc-y += xilinx_ethlite.o +# LM32 boards +obj-lm32-y += lm32_boards.o + # LM32 peripherals obj-lm32-y += lm32_pic.o obj-lm32-y += lm32_pic_cpu.o diff --git a/default-configs/lm32-softmmu.mak b/default-configs/lm32-softmmu.mak new file mode 100644 index 0000000..ab774a2 --- /dev/null +++ b/default-configs/lm32-softmmu.mak @@ -0,0 +1,4 @@ +# Default configuration for lm32-softmmu + +CONFIG_PTIMER=y +CONFIG_PFLASH_CFI02=y diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c new file mode 100644 index 0000000..c174c17 --- /dev/null +++ b/hw/lm32_boards.c @@ -0,0 +1,295 @@ +/* + * QEMU models for LatticeMico32 uclinux and evr32 boards. + * + * Copyright (c) 2010 Michael Walle + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "sysbus.h" +#include "hw.h" +#include "net.h" +#include "flash.h" +#include "sysemu.h" +#include "devices.h" +#include "boards.h" +#include "loader.h" +#include "blockdev.h" +#include "elf.h" +#include "lm32_hwsetup.h" +#include "lm32.h" + +struct reset_info { + CPUState *env; + uint32_t bootstrap_pc; + uint32_t flash_base; + uint32_t hwsetup_base; + uint32_t initrd_base; + uint32_t initrd_size; + uint32_t cmdline_base; +}; + +qemu_irq *lm32_pic_init_cpu(CPUState *env); + +static void main_cpu_reset(void *opaque) +{ + struct reset_info *reset_info = opaque; + CPUState *env = reset_info->env; + + cpu_reset(env); + + /* init defaults */ + env->pc = reset_info->bootstrap_pc; + env->regs[R_R1] = reset_info->hwsetup_base; + env->regs[R_R2] = reset_info->cmdline_base; + env->regs[R_R3] = reset_info->initrd_base; + env->regs[R_R4] = reset_info->initrd_base + reset_info->initrd_size; + env->eba = reset_info->flash_base; + env->deba = reset_info->flash_base; +} + +static void lm32_evr_init(ram_addr_t ram_size_not_used, + const char *boot_device, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + CPUState *env; + DriveInfo *dinfo; + ram_addr_t phys_ram; + ram_addr_t phys_flash; + qemu_irq *cpu_irq, irq[32]; + DeviceState *dev; + struct reset_info *reset_info; + int i; + + /* memory map */ + ram_addr_t flash_base = 0x04000000; + size_t flash_sector_size = 256 * 1024; + size_t flash_size = 32 * 1024 * 1024; + ram_addr_t ram_base = 0x08000000; + size_t ram_size = 64 * 1024 * 1024; + ram_addr_t timer0_base = 0x80002000; + ram_addr_t uart0_base = 0x80006000; + ram_addr_t timer1_base = 0x8000a000; + int uart0_irq = 0; + int timer0_irq = 1; + int timer1_irq = 3; + + reset_info = qemu_mallocz(sizeof(struct reset_info)); + + if (cpu_model == NULL) { + cpu_model = "lm32-full"; + } + env = cpu_init(cpu_model); + reset_info->env = env; + + reset_info->flash_base = flash_base; + + phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size); + cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); + + phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size); + dinfo = drive_get(IF_PFLASH, 0, 0); + /* Spansion S29NS128P */ + pflash_cfi02_register(flash_base, phys_flash, + dinfo ? dinfo->bdrv : NULL, flash_sector_size, + flash_size / flash_sector_size, 1, 2, + 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); + + cpu_irq = lm32_pic_init_cpu(env); + dev = lm32_pic_init(env, *cpu_irq); + for (i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in(dev, i); + } + + sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]); + sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]); + sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]); + + /* make sure juart isn't the first chardev */ + lm32_juart_init(env); + + reset_info->bootstrap_pc = flash_base; + + if (kernel_filename) { + uint64_t entry; + int kernel_size; + + kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL, + 1, ELF_MACHINE, 0); + reset_info->bootstrap_pc = entry; + + if (kernel_size < 0) { + kernel_size = load_image_targphys(kernel_filename, ram_base, + ram_size); + reset_info->bootstrap_pc = ram_base; + } + + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } + } + + qemu_register_reset(main_cpu_reset, reset_info); +} + +static void lm32_uclinux_init(ram_addr_t ram_size_not_used, + const char *boot_device, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, const char *cpu_model) +{ + CPUState *env; + DriveInfo *dinfo; + ram_addr_t phys_ram; + ram_addr_t phys_flash; + qemu_irq *cpu_irq, irq[32]; + DeviceState *dev; + struct hwsetup *hw; + struct reset_info *reset_info; + int i; + + /* memory map */ + ram_addr_t flash_base = 0x04000000; + size_t flash_sector_size = 256 * 1024; + size_t flash_size = 32 * 1024 * 1024; + ram_addr_t ram_base = 0x08000000; + size_t ram_size = 64 * 1024 * 1024; + ram_addr_t uart0_base = 0x80000000; + ram_addr_t timer0_base = 0x80002000; + ram_addr_t timer1_base = 0x80010000; + ram_addr_t timer2_base = 0x80012000; + int uart0_irq = 0; + int timer0_irq = 1; + int timer1_irq = 20; + int timer2_irq = 21; + ram_addr_t hwsetup_base = 0x0bffe000; + ram_addr_t cmdline_base = 0x0bfff000; + ram_addr_t initrd_base = 0x08400000; + size_t initrd_max = 0x01000000; + + reset_info = qemu_mallocz(sizeof(struct reset_info)); + + if (cpu_model == NULL) { + cpu_model = "lm32-full"; + } + env = cpu_init(cpu_model); + reset_info->env = env; + + reset_info->flash_base = flash_base; + + phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size); + cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); + + phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size); + dinfo = drive_get(IF_PFLASH, 0, 0); + /* Spansion S29NS128P */ + pflash_cfi02_register(flash_base, phys_flash, + dinfo ? dinfo->bdrv : NULL, flash_sector_size, + flash_size / flash_sector_size, 1, 2, + 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); + + cpu_irq = lm32_pic_init_cpu(env); + dev = lm32_pic_init(env, *cpu_irq); + for (i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in(dev, i); + } + + sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]); + sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]); + sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]); + sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]); + + /* make sure juart isn't the first chardev */ + lm32_juart_init(env); + + reset_info->bootstrap_pc = flash_base; + + if (kernel_filename) { + uint64_t entry; + int kernel_size; + + kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL, + 1, ELF_MACHINE, 0); + reset_info->bootstrap_pc = entry; + + if (kernel_size < 0) { + kernel_size = load_image_targphys(kernel_filename, ram_base, + ram_size); + reset_info->bootstrap_pc = ram_base; + } + + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + kernel_filename); + exit(1); + } + } + + /* generate a rom with the hardware description */ + hw = hwsetup_init(); + hwsetup_add_cpu(hw, "LM32", 75000000); + hwsetup_add_flash(hw, "flash", flash_base, flash_size); + hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size); + hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq); + hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq); + hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq); + hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq); + hwsetup_add_trailer(hw); + hwsetup_create_rom(hw, hwsetup_base); + hwsetup_free(hw); + + reset_info->hwsetup_base = (uint32_t)hwsetup_base; + + if (kernel_cmdline && strlen(kernel_cmdline)) { + pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, + kernel_cmdline); + reset_info->cmdline_base = (uint32_t)cmdline_base; + } + + if (initrd_filename) { + size_t initrd_size; + initrd_size = load_image_targphys(initrd_filename, initrd_base, + initrd_max); + reset_info->initrd_base = (uint32_t)initrd_base; + reset_info->initrd_size = (uint32_t)initrd_size; + } + + qemu_register_reset(main_cpu_reset, reset_info); +} + +static QEMUMachine lm32_evr_machine = { + .name = "lm32-evr", + .desc = "LatticeMico32 EVR32 eval system", + .init = lm32_evr_init, + .is_default = 1 +}; + +static QEMUMachine lm32_uclinux_machine = { + .name = "lm32-uclinux", + .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems", + .init = lm32_uclinux_init, + .is_default = 0 +}; + +static void lm32_machine_init(void) +{ + qemu_register_machine(&lm32_uclinux_machine); + qemu_register_machine(&lm32_evr_machine); +} + +machine_init(lm32_machine_init);