Patchwork [14/17] lm32: todo and documentation

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Submitter Michael Walle
Date Feb. 10, 2011, 11:12 p.m.
Message ID <1297379530-23487-15-git-send-email-michael@walle.cc>
Download mbox | patch
Permalink /patch/82685/
State New
Headers show

Comments

Michael Walle - Feb. 10, 2011, 11:12 p.m.
This patch adds general target documentation and a todo list.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 target-lm32/README |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 target-lm32/TODO   |    3 +++
 2 files changed, 49 insertions(+), 0 deletions(-)
 create mode 100644 target-lm32/README
 create mode 100644 target-lm32/TODO
Blue Swirl - Feb. 11, 2011, 8:41 p.m.
On Fri, Feb 11, 2011 at 1:12 AM, Michael Walle <michael@walle.cc> wrote:
> This patch adds general target documentation and a todo list.
>
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  target-lm32/README |   46 ++++++++++++++++++++++++++++++++++++++++++++++
>  target-lm32/TODO   |    3 +++
>  2 files changed, 49 insertions(+), 0 deletions(-)
>  create mode 100644 target-lm32/README
>  create mode 100644 target-lm32/TODO
>
> diff --git a/target-lm32/README b/target-lm32/README
> new file mode 100644
> index 0000000..a1c2c7e
> --- /dev/null
> +++ b/target-lm32/README
> @@ -0,0 +1,46 @@
> +LatticeMico32 target
> +--------------------
> +
> +General
> +-------
> +All opcodes including the JUART CSRs are supported.
> +
> +
> +JTAG UART
> +---------
> +JTAG UART is routed to a serial console device. For the current boards it
> +is the second one. Ie to enable it in the qemu virtual console window use
> +the following command line parameters:
> +  -serial vc -serial vc
> +This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
> +available as virtual consoles.
> +
> +
> +Programmatically terminate the emulator
> +----------------------------------------
> +Originally neither the LatticeMico32 nor its peripherals support a
> +mechanism to shut down the machine. Emulation aware programs can write to a
> +to a special register within the system control block to shut down the
> +virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
> +first BSP which instantiate this model. A (32 bit) write to 0xfff0000
> +causes a vm shutdown.
> +
> +
> +Special instructions
> +--------------------
> +The translation recognizes one special instruction to halt the cpu:
> +  and r0, r0, r0
> +On real hardware this instruction is a nop. It is not used by GCC and
> +should (hopefully) not be used within hand-crafted assembly.
> +Insert this instruction in your idle loop to reduce the cpu load on the
> +host.

It would be better to use MMIO or privileged instruction for this
instead of changing an unprivileged instruction.
Michael Walle - Feb. 11, 2011, 10:45 p.m.
Am Freitag 11 Februar 2011, 21:41:14 schrieb Blue Swirl:
> > +Special instructions
> > +--------------------
> > +The translation recognizes one special instruction to halt the cpu:
> > +  and r0, r0, r0
> > +On real hardware this instruction is a nop. It is not used by GCC and
> > +should (hopefully) not be used within hand-crafted assembly.
> > +Insert this instruction in your idle loop to reduce the cpu load on the
> > +host.
> 
> It would be better to use MMIO or privileged instruction for this
> instead of changing an unprivileged instruction.

MMIO can't be used as that would have an impact on real hardware? The idea is 
to use this instruction for both the real hardware and QEMU.
Blue Swirl - Feb. 12, 2011, 8 a.m.
On Sat, Feb 12, 2011 at 12:45 AM, Michael Walle <michael@walle.cc> wrote:
> Am Freitag 11 Februar 2011, 21:41:14 schrieb Blue Swirl:
>> > +Special instructions
>> > +--------------------
>> > +The translation recognizes one special instruction to halt the cpu:
>> > +  and r0, r0, r0
>> > +On real hardware this instruction is a nop. It is not used by GCC and
>> > +should (hopefully) not be used within hand-crafted assembly.
>> > +Insert this instruction in your idle loop to reduce the cpu load on the
>> > +host.
>>
>> It would be better to use MMIO or privileged instruction for this
>> instead of changing an unprivileged instruction.
>
> MMIO can't be used as that would have an impact on real hardware? The idea is
> to use this instruction for both the real hardware and QEMU.

Then it's OK. In general, if this were a QEMU only solution (like I
thought), then new instruction would have been a bit less attractive
than MMIO, which can be ignored on real HW, remapped by a kernel with
MMU (which you don't have) etc.

Patch

diff --git a/target-lm32/README b/target-lm32/README
new file mode 100644
index 0000000..a1c2c7e
--- /dev/null
+++ b/target-lm32/README
@@ -0,0 +1,46 @@ 
+LatticeMico32 target
+--------------------
+
+General
+-------
+All opcodes including the JUART CSRs are supported.
+
+
+JTAG UART
+---------
+JTAG UART is routed to a serial console device. For the current boards it
+is the second one. Ie to enable it in the qemu virtual console window use
+the following command line parameters:
+  -serial vc -serial vc
+This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
+available as virtual consoles.
+
+
+Programmatically terminate the emulator
+----------------------------------------
+Originally neither the LatticeMico32 nor its peripherals support a
+mechanism to shut down the machine. Emulation aware programs can write to a
+to a special register within the system control block to shut down the
+virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
+first BSP which instantiate this model. A (32 bit) write to 0xfff0000
+causes a vm shutdown.
+
+
+Special instructions
+--------------------
+The translation recognizes one special instruction to halt the cpu:
+  and r0, r0, r0
+On real hardware this instruction is a nop. It is not used by GCC and
+should (hopefully) not be used within hand-crafted assembly.
+Insert this instruction in your idle loop to reduce the cpu load on the
+host.
+
+
+Ignoring the MSB of the address bus
+-----------------------------------
+Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
+area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
+0x80000000-0xffffffff is not cached and used to access IO devices. This
+behaviour can be enabled with:
+  cpu_lm32_set_phys_msb_ignore(env, 1);
+
diff --git a/target-lm32/TODO b/target-lm32/TODO
new file mode 100644
index 0000000..b9ea0c8
--- /dev/null
+++ b/target-lm32/TODO
@@ -0,0 +1,3 @@ 
+* disassembler (lm32-dis.c)
+* linux-user emulation
+* native bp/wp emulation (?)