| Message ID | 201102101941.p1AJfTtM003386@greed.delorie.com |
|---|---|
| State | New |
| Headers | show |
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 02/10/11 12:41, DJ Delorie wrote: > CSA sometimes moves insns between a compare and its branch, as CSA > happens after split2. This patch disables CSA until m32c's flags > tracking and compare optimization can be rewritten, but that's too big > a change for stage4. Applied. > > * config/m32c/m32c.c (m32c_option_override): Disable > -fcombine-stack-adjustments until flag value tracking and compare > optimization can be rewritten. Rather than doing this in m32.c, why not do it for all cc0 targets in the generic part of the compiler. Or twiddle the csa code itself to do nothing if HAVE_cc0? If csa is moving insns between the cc0 setter & user, then it's going to break more than just the m32c. jeff -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJNWo8MAAoJEBRtltQi2kC731AH/3crnzslh6sleCnt0sSpJWhM Q7g55Pcf6YF8vgh2BhQRu+q9CEqu5M+KyMHu2IV2Pyx1nRPHUUOzu05C1fsfWs6r 5Kc5VYWDj74LxlkqxZGGt6KmA5yBSF9XkvoKrYQp57HHZzxa3ZLiZe1OadFSEoDp L9fVxOIQpl2mqvR3KByTd3miGyNFzVRVs3qF6W+DTwMQt2TSKNt8r8HWaisMhBDa lGotHerPnkGUKLI2vewYSBGTo776iT2VKsyXGQSte7B2mee1nsam2CxY3eQxiAXS NrBlNPrMD1jBfHOR1mQ9jozYyLNud6kJ31/FahQv8FDpNLZutP3Pmw2i1J0WMqU= =zPX1 -----END PGP SIGNATURE-----
> Rather than doing this in m32.c, why not do it for all cc0 targets > in the generic part of the compiler. Or twiddle the csa code itself > to do nothing if HAVE_cc0? m32c is not a cc0 target, it has a flags register. However, until now, I didn't need to track clobbers to the flags register since I kept compares and branches as one insn until split2. I'll need to rethink the whole thing after 4.6 branches.
Index: config/m32c/m32c.c =================================================================== --- config/m32c/m32c.c (revision 170020) +++ config/m32c/m32c.c (working copy) @@ -451,12 +451,17 @@ m32c_option_override (void) flag_strict_volatile_bitfields = 1; /* r8c/m16c have no 16-bit indirect call, so thunks are involved. This is always worse than an absolute call. */ if (TARGET_A16) flag_no_function_cse = 1; + + /* This wants to put insns between compares and their jumps. */ + /* FIXME: The right solution is to properly trace the flags register + values, but that is too much work for stage 4. */ + flag_combine_stack_adjustments = 0; } #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m32c_override_options_after_change static void